Author Topic: Working on a full logic UD3 driver  (Read 112 times)

Offline Nijin

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Working on a full logic UD3 driver
« on: May 04, 2019, 08:22:32 PM »
Hello guys, I want to use a skip pulse driver for my Tesla but I'm lazy to design and programming a CPLD driver :p . So I decided to create a skip pulse driver for full bridge drsstc without any programmable devices.
I found peoples who already worked on a logic skip pulse driver ( https://4hv.org/e107_plugins/forum/forum_viewtopic.php?p=1&id=178230#post-178230 and https://highvoltageforum.net/index.php?topic=346.20 ) but I don't understand how they work.

First I begin with the logic of the UD2.7 driver and I added 2 D flip flop. It seems to work on simulation  :D : http://tinyurl.com/yyan2agj


But i have a question about the switching of IGBT : How the driver generate the dead time to not short-circuit the half bridge module ? I didn't find any information on the UD2.7 drive about dead-time generation but I'm using it and it works so I believe it have dead time...


And if you have some advices to improve the skip pulse logic of my driver It will be usefull  :) thank you !
Everything is a fuse if you pass enough current

Offline dexter

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Re: Working on a full logic UD3 driver
« Reply #1 on: May 04, 2019, 09:12:54 PM »
I too didn't understood exactly how UD2.9 works so i made it on a bread board (just the 74HC74 74HC08 74HC14 chips and the passives) feed it signals for FB OCD Interrupter and it works as advertised.
J16 open - works like UD2.7
J16 closed - no output for the duration of the OCD


yellow trace - intrerupter
green trace - output of one of the 74HC08 gates before the UCC

How the driver generate the dead time?
It doesn't. The signal that goes to the GDT comes from the Q and Q- of the comparator which are 50% duty cycle signals and no disproportionate delays seem to be added on the UCC and on the power stage
« Last Edit: May 04, 2019, 09:14:45 PM by dexter »

Offline profdc9

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Re: Working on a full logic UD3 driver
« Reply #2 on: May 05, 2019, 09:11:40 PM »
The UD2.9 changes the way that the UD2.7C works.  I modeled it in Qucs (Quite Universal Circuit Simulation) and I attached the schematic below and show the screenshot.

The way it works is a little different than the UD2.7C.  In the UD2.7C (see schematic below), the overcurrent condition clears the second D-latch U7B unconditionally.  This latch output Q is ANDed at U5D, goes through a double NOT gates U8D/U8E and clears U7A, and then is ANDed with the TL3116 outputs at U5B/U5C to turn off the drivers.  The latch U7B can only be reset by another interrupter edge, so once the overcurrent condition happens during a pulse, the driver stays shut off until the interrupter edge reoccurs.

The UD2.9C on the other hand works like this:  When an interrupter pulse comes in at U8C, the diode/capacitor network causes a brief low edge signal.  This sets BOTH U7A/U7B and allows pulses to start.  If J16 is open for not skip pulse operation, when the overcurrent condition occurs, U7A is cleared.  This in turn takes a path through U5B, U8D, U8E, and then resets U7B, similar to what happens in the UD2.7C.  U7A and U7B can only be set again by the rising edge of another interrupter pulse, and so the behavior is the same as the non skip pulse, even though it is arranged a little different.

If J16 is closed, then while the current in the primary is ringing down, once the overcurrent condition clears, the signal from U4 Q is conducted through J16 and allows U7A to be set.  This turns on U7A Q and then if the interrupter pulse is still continuing, the output of U5B is high and so the signal is also clocked in on U7B, reenabling both D-latches and so the driver turns back on until either the overcurrent occurs and U7A/U7B are shut off again, or the interrupter pulse terminates and the output of U5B is low and shuts off U7B.    One other feature is the presence of the transistor Q5.  This transistor prevents another interrupter pulse edge from turning the driver back on if there if at that moment there is an overcurrent condition, so one can not force the driver on excessively and risk damaging the transistors with excessive current.

Typically I don't get a problem with dead time because I use a gate driver transformer to drive the upper and lower transistors with opposite polarity windings.

You can take a look at the simulation below where I verified I could turn the skip pulse on or off depending the connection of the jumper.

Dan



Hello guys, I want to use a skip pulse driver for my Tesla but I'm lazy to design and programming a CPLD driver :p . So I decided to create a skip pulse driver for full bridge drsstc without any programmable devices.
I found peoples who already worked on a logic skip pulse driver ( https://4hv.org/e107_plugins/forum/forum_viewtopic.php?p=1&id=178230#post-178230 and https://highvoltageforum.net/index.php?topic=346.20 ) but I don't understand how they work.

First I begin with the logic of the UD2.7 driver and I added 2 D flip flop. It seems to work on simulation  :D : http://tinyurl.com/yyan2agj


But i have a question about the switching of IGBT : How the driver generate the dead time to not short-circuit the half bridge module ? I didn't find any information on the UD2.7 drive about dead-time generation but I'm using it and it works so I believe it have dead time...


And if you have some advices to improve the skip pulse logic of my driver It will be usefull  :) thank you !

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Re: Working on a full logic UD3 driver
« Reply #2 on: May 05, 2019, 09:11:40 PM »

 


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