Author Topic: UD2.9 skip pulse assembled  (Read 3398 times)

Offline profdc9

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Re: UD2.9 skip pulse assembled
« Reply #20 on: May 24, 2018, 04:22:00 PM »
With the pulse skipping, the OCD is triggered all of the time.  Rather than set the OCD to trigger at a high current, say 500 A, I set it to about half that, or 250 A.  After the OCD is triggered, there is a flip flop that is cleared and shuts off the bridge for the next cycle.  If the OCD does not reoccur during that cycle, the bridge is turned back on at the next rising edge.  So really it should be called "cycle skip" because a low and a high transition must both be skipped to prevent flux imbalance from accumulating on the gate drive transformer.

I have seen similar spark lengths both with and without pulse skipping, but the power available to my coil is not that great, since I currently only have 15-20 A and 120 VAC to work with, before the lousy power factor is accounted for, so perhaps only 1 kW of actual delivered power.  The idea is to deliver power more continuously during the whole burst rather than only briefly at the end of the burst before the overcurrent trips.  There is probably some compromise pulse length that achieves a good arc length while minimally stressing the IGBTs.  Short pulse lengths can achieve good results but high peak currents shorten the life of the IGBTs.  Long pulse lengths can work too, but non-interrupted SSTCs definitely underperform interrupted DRSSTCs.  QCW systems have low duty cycle but very long ramp-up time (millisecond scale).  The idea behind pulse skipping is that it allows one to lower the current and increase the peak current time.  This strategy is probably good to a limited extent, but if the peak current is too low then the arc length is likely going to be reduced.  I have not yet figured out the compromise, but the UD2.9 controller is going to help do that.  I designed a new interrupter for the purpose of exploring these issues and I am waiting for the PCB to be manufactured.  The new interrupter has two selectable pulse width lengths as well as bps length, and also interrupts on the peak of the AC cycle to try to improve power factor and allow burst duty cycle control, and so I should be able to try longer pulse lengths (I am currenly limited to about 160 microseconds).  This interrupter is in the DRSSTC pack and you can look at the schematic if you wish.

Dan

Offline Uspring

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Re: UD2.9 skip pulse assembled
« Reply #21 on: May 25, 2018, 12:00:00 PM »
Thank you for your answer.

A burst length of 160us might be too short to take notice the effect of the arc limiting primary current significantly. So likely you will notice pulse skipping up to the end of the burst.

Quote
Short pulse lengths can achieve good results but high peak currents shorten the life of the IGBTs.  Long pulse lengths can work too, but non-interrupted SSTCs definitely underperform interrupted DRSSTCs.  QCW systems have low duty cycle but very long ramp-up time (millisecond scale).

"Underperform" depends on how you define power input. In terms of line power requirements long bursts are costly. But if you relate arc length to power during the burst, QCWs are very effective. My DRSSTC can create a 2m arc form a 320V 700A input, while Loneoceans QCW1.5 can reach almost that size (1.75m) with a 300V and 150A source.

There is a large unexplored region of intermediate length bursts nicely accessible with pulse skip technology.

Offline Teravolt

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Re: UD2.9 skip pulse assembled
« Reply #22 on: May 25, 2018, 08:52:38 PM »
hi profdc9, are you counting the cycles to know when to retrigger the pulse skipping or are you retriggering based on the current level? are you using a microprocessor to manage? 

Offline profdc9

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Re: UD2.9 skip pulse assembled
« Reply #23 on: May 25, 2018, 09:43:13 PM »
The schematic of the pulse skip is below.

It is a small modification of the UD2.7C interrupter.  Whereas on the UD2.7C interrupter an overcurrent event clears the overcurrent flip-flop and can only be set again by another interrupter rising edge, the UD2.9 is selectable to that each rising edge of the current, the flip-flop is set.  If the overcurrent does not reoccur, the enable flip-flop is set and the gate driver turns back on.  The jumper J16 closed allows the rising edge of the current to set the flip-flop.  If it is closed, the flip-flop can only be set again by the interrupter rising edge, which is the old behavior.

So no microprocessor is required, it is just a simple modification of the UD2.7C driver.

Dan

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Re: UD2.9 skip pulse assembled
« Reply #23 on: May 25, 2018, 09:43:13 PM »

 


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