Full Bridge SSTC

[ZakW]

Starting a new thread since this is a different issue and no longer a half bridge.

Using Steve's schematic - https://www.stevehv.4hv.org/SSTC2/SSTC2-03.gif

Bridge components:
5R gate resistors
IRFP460's
https://www.mouser.com/ProductDetail/78-VS-E5TX1506-M3 - Gate/Source diodes
https://www.mouser.com/ProductDetail/505-M10.68-1600-10 - giant DC blocking cap

Getting straight to it - from what I can tell my MOSFETs are not turning on or they are but for a very short time...

Purple = Gate signal
Yellow = Drain signal

I scoped each FET and they all had the same looking signal for both Vgs and Vds.

in phase - makes arcs

flipped GDT phasing (flipped at driver)


The coil runs! At 30v I get a weak output but it also changes when I bring my hand near it. The arcs grow then get thin and light blue. I have also tested halfwave mains up to 120v and for a short time (depending on my hand placement) was getting 10in arcs. It was very unstable and something was clearly not running properly.

I worked 11 hours assembling and troubleshooting yesterday and about 10 hours troubleshooting today. I quadrupled checked everything I can think of, starting to consider just sticking with an H-bridge but I have to know what is happening.

Here is what the UCC outputs look like. They look bad. Without the bridge powered up they look a lot better. They still have ringing but are more square.



Referencing Richie's site - http://www.richieburnett.co.uk/temp/gdt/gdt2.html

I think my Vgs looks good. However, the 'out of phase' picture looks a lot like the 'sharkfin' example.

Here is my GDT:



The leads are extra long in this picture. I made sure to keep track of which leads were on which side. Per Steve's schematic, I phased it so that Q1 and Q4 are both 'marked' leads and Q2 and Q3 are the unmarked leads.

General setup and pictures of the bridge:









Any suggestions would be greatly appreciated.

Thank you.

[ZakW]

Update: I got the half bridge and full bridge working.

I created a small board for two 1uf caps in parallel for a total of 2uf as well as two 47uf electrolytic capacitors back to back per this site http://www.imajeenyus.com/electronics/20141006_gdt_testing/index.shtml The idea being that the electrolytic caps would help with ringing.

Unresolved issues:
1. Uneven gate voltage on Q1 vs Q2 in a half bridge configuration. I am sure it is the same for the full bridge but I was unable to scope every FET tonight. I have no idea what would cause an imbalance like this.

2. The full bridge will not work when the CT is connected. It doesnt matter which why it is connected. I was able to power the coil up to 120v with out the CT. I assume the EMI is impacting the driver... What is even more strange is the half bridge worked with the CT plugged in. Although the breakout was uneven and sporadic at times.

3. I tried connecting pins 1&2 of the HC14 with a resistor to kick start oscillations but it did not seem to have an impact on making the coil run consistently.

4. The high speed diode across drain and source of Q4 was getting hot during short durations. I read that they protect FETs from transient gate over-voltage but I am not sure what would cause that scenario.

5. The Vds signal still looks the same, at least on the FETs I scoped ( see pictures below). Could they shutting off to quickly due to noise on my GDT signal?

Other than those 5 things, I plan on reducing the length of my GDT leads now that I have things in somewhat of a working configuration.

end of update.
__________________________________________________


I did a lot more testing and think I have made some progress and narrowed down what is going on.

**Biggest change I made was swapping the .1uf DC blocking capacitor (c6 in Mini) with a 1uf cap. That improved the gate drive signal and fixed the low inductance looking output signal.
Using Steve's mini SSTC design to drive the full bridge as well as the half bridge. https://www.stevehv.4hv.org/SSTC5/miniSSTCfnlsch.JPG. **

Rather than take apart and rebuild the full bridge to rule out if that was the issue or not I decided to lash up a new half bridge with the same design (attached pictures below). This was before I figured out the DC blocking cap was too low.

My question now is, are the MOSFET's damaged from this? When I first powered up the half bridge I got decent arcs from the 30v input but after a few minutes went by the output significantly decreased. Now it is just a tiny 2mm spark. What would cause the decline in output? I am not sure in what way a MOSFET could be damaged to have that happen.

Here is what the Vgs/Vds signals looked like on the half bridge with new FETs for ~30sec after powering it on.. (still using the .1uf cap at this point!)

Purple = Vgs signal Yellow = Vds

Decent gate signal, with some ringing on the drain.



This was the other MOSFET shortly after moving the probes over

Worse gate signal (only moments after testing the first FET) and even worse ringing on the drain.


I rewound a new GDT thinking that might improve the signal and added more turns

OLD GDT with 14T

New GDT with 20T


I was still getting the same low inductance signal. The core material is appropriate and these GDTs have worked just fine before.

Results after increasing the UCC gate drive DC blocking cap to 1uf


Here is what Q1 Vgs/Vds signals look like now
purple = Vgs Yellow = Vds



Here is what Q2 Vgs/Vds signals look like now: The Vgs signal is only +-7v... what would cause the voltage to sag on one MOSFET compared to the other? Could it be damaged in some way that is causing the voltage to sag?




General pictures of the half bridge and driver.







Since this is a thread to troubleshoot my full bridge I will resume troubleshooting it now that I have made a some progress on correcting the UCC output. I assume it is likely that some of the MOSFETs are damaged and will need to be replaced.

I also found Dave's response about DC blocking capacitor values https://highvoltageforum.net/index.php?topic=834.0.msg5556#msg5556

Just realized, 0.1uF is not enough for driving your four IGBTs.  Thier total gate capacitance is ~66nF (0.066uF).  That explains almost all of the gate-voltage drop when loaded (when IGBTs are connected).  It's forming a capacitive divider of 0.1uF and 0.066uF.  To avoid much voltage drop, C6 should be much larger than the total gate capacitance, at least 1uF in your case.  2.2uF would be better.

I will add a sperate breakout board for the DC blocking caps as there is not enough room with my current layout.

[davekni]

I scoped each FET and they all had the same looking signal for both Vgs and Vds.

in phase - makes arcs

flipped GDT phasing (flipped at driver)

I'd guess that GDT output phasing isn't correct.  Even though you constructed it carefully, I'd double-check phasing with your scope.  Easy to do with no Vbus power, one scope channel on driver output (GDT primary) and other channel on one FET at a time.  GDT construction looks good.  Doubt any more turns are needed.  Excess turns increases leakage inductance, so can be worse.

Also, as I posted on your other thread, you need a snubber capacitor from Vbus+ to Vbus- at the H-Bridge.  Wiring inductance on Vbus DC power is part of the issue here too.

I created a small board for two 1uf caps in parallel for a total of 2uf as well as two 47uf electrolytic capacitors back to back per this site http://www.imajeenyus.com/electronics/20141006_gdt_testing/index.shtml The idea being that the electrolytic caps would help with ringing.

Yes, that should work well.  Or just the two 1uF caps with a resistor in series with one of the two for damping.  See UD2.7 schematics for ideas.  Your existing version with electrolytics is just fine, so no need to change this part.

I rewound a new GDT thinking that might improve the signal and added more turns

I think your original GDT is better.  The four parallel primary leads reduce parasitic inductance.

Here is what Q2 Vgs/Vds signals look like now: The Vgs signal is only +-7v... what would cause the voltage to sag on one MOSFET compared to the other? Could it be damaged in some way that is causing the voltage to sag?

Yes.  Two possible issues come to mind.  First (most likely) is a damaged FET gate.  Excess Vgs (from ESD or switching transient) can cause gate oxide punch-through, resulting in a low resistance from gate to source.  Measure with a DC ohm meter (with driver and bridge power off).  FET gate-source should be high impedance.  If in-circuit, you should see just your intentional 5ohm (or was it 10ohm) series resistor.  If one FET has lower resistance, it needs replacing.
Other possibility is that you have a scope ground loop.  Connecting scope probe ground clip to a high-side FET can cause problems.  Definitely is a problem if bridge power source is also grounded.

I also found Dave's response about DC blocking capacitor values https://highvoltageforum.net/index.php?topic=834.0.msg5556#msg5556

Quote

    Just realized, 0.1uF is not enough for driving your four IGBTs.  Thier total gate capacitance is ~66nF (0.066uF).  That explains almost all of the gate-voltage drop when loaded (when IGBTs are connected).  It's forming a capacitive divider of 0.1uF and 0.066uF.  To avoid much voltage drop, C6 should be much larger than the total gate capacitance, at least 1uF in your case.  2.2uF would be better.


I will add a separate breakout board for the DC blocking caps as there is not enough room with my current layout.

Your earlier solution with back-to-back electrolytic caps is fine too.  Or, two film caps with a resistor in series with one (as in UD2.7 output to GDT) is good.  Either is better than just 2.2uF or just 1.0uF, but even those plain capacitors will likely be sufficient.

[ZakW]

I was messing with the full bridge and managed to pop Q4. The diode across drain and source was getting pretty warm. On a short higher voltage run Q4 popped. It also killed the resistor on the gate... After replacing the FET and gate resistor I was getting small output at 30v(used for testing). I scoped Q4 and was seeing a 70V DC signal on Vds with sharp dips at each GDT pulse to the gate. I may have damaged another FET when it originally died, I will have to take the bridge apart and check later.

Afterwards I swapped my half bridge in to continue testing the feedback issues. Getting decent results I flew to close to the sun with only 2 primary turns and killed another FET.

It was time to call it a night. However, I did learn a few things. See below:

I'd guess that GDT output phasing isn't correct.  Even though you constructed it carefully, I'd double-check phasing with your scope.  Easy to do with no Vbus power, one scope channel on driver output (GDT primary) and other channel on one FET at a time.  GDT construction looks good.  Doubt any more turns are needed.  Excess turns increases leakage inductance, so can be worse.

Also, as I posted on your other thread, you need a snubber capacitor from Vbus+ to Vbus- at the H-Bridge.  Wiring inductance on Vbus DC power is part of the issue here too.

I wound a new CT (50T on T35 ferrite) using a core material that I know is suitable (same as my GDT core). That way I could rule out bad CT core material. Still did not improve the consistency of the feedback signal to power the coil.
I have tried swapping the phase of the CT and it results in zero output. I will use my scope to verify phasing next time.

 [ You are not allowed to view attachments ]

I would like to review the CT's input to the 74HC14. I have seen several different versions so far and I am not sure why specific component values are chosen and why different topologies are selected over the other. I know Steve's Mini was designed to use an antenna but I have also gotten it to work with a CT. But other times it has been problematic. I know the nature of receiving a feedback signal next to a TC that is outputting a lot of EMI can be tricky but it seems too inconsistent.

Examples:
https://circuitsaladdotcom.files.wordpress.com/2021/05/pcb-tesla-coil.jpg
https://www.stevehv.4hv.org/SSTC5/miniSSTCfnlsch.JPG
https://www.loneoceans.com/labs/sstc2/sstc2schematicv10.jpg

This leads me to think that there is room for improvement compared to my current layout. Does anything stand out to from the schematics I linked above?
Here is the schematic I am using: except for the 22k resistor.

 [ You are not allowed to view attachments ]

Yes, that should work well.  Or just the two 1uF caps with a resistor in series with one of the two for damping.  See UD2.7 schematics for ideas.  Your existing version with electrolytics is just fine, so no need to change this part.

I did notice an improved Vds signal (reduced ringin) on my half bridge using a 1uf capacitor across Vbus+-. If I increased the value too much while using halfwave mains I would get a loud popping in the arc vs the quiet VTTC sound that the staccato normally provides. I will stick with ~1uf.

Yes.  Two possible issues come to mind.  First (most likely) is a damaged FET gate.  Excess Vgs (from ESD or switching transient) can cause gate oxide punch-through, resulting in a low resistance from gate to source.  Measure with a DC ohm meter (with driver and bridge power off).  FET gate-source should be high impedance.  If in-circuit, you should see just your intentional 5ohm (or was it 10ohm) series resistor.  If one FET has lower resistance, it needs replacing.
Other possibility is that you have a scope ground loop.  Connecting scope probe ground clip to a high-side FET can cause problems.  Definitely is a problem if bridge power source is also grounded.

I have only been using my scope with my DC supply since I learned the variac was connected to line.

I had a feeling it was some sort of damage to the gate causing the voltage to drop. I wonder if during my initial tests with the full bridge damaged other MOSFETs as well. I will have to check when I have more time.

Your earlier solution with back-to-back electrolytic caps is fine too.  Or, two film caps with a resistor in series with one (as in UD2.7 output to GDT) is good.  Either is better than just 2.2uF or just 1.0uF, but even those plain capacitors will likely be sufficient.

To my surprise there really is not a lot of information out there (at least that I could find on google) about the DC blocking cap for the drive chips/GDT. I just see a lot of "XXuf amount should be good" "no, you need at least XXuf"... You did have an explanation on a thread where you went into detail about using a .1uf cap to power an IGBT full bridge and how it would essentially cause a voltage drop to the overall GDT gate signal voltage since .1uf was too low. That was a helpful explanation.

I really want to work out the CT/feedback issues so that I know its not hard switch/inconsistent timing that is going to lead to the bridge failing. I ordered a function generator that I can use for testing. Should be here in 3-4 days.

Is there a good way to use the function generator to induce a signal into the CT (400kHz) so I can mimic when the TC is running? That way I can use my scope to see how the CT signal is processed by the rest of the components. Is it as simple as rapping a few turns around the CT or will the voltage be too low considered the TC secondary voltage is much higher?

[davekni]

I would like to review the CT's input to the 74HC14. I have seen several different versions so far and I am not sure why specific component values are chosen and why different topologies are selected over the other. I know Steve's Mini was designed to use an antenna but I have also gotten it to work with a CT. But other times it has been problematic. I know the nature of receiving a feedback signal next to a TC that is outputting a lot of EMI can be tricky but it seems too inconsistent.

Examples:
https://circuitsaladdotcom.files.wordpress.com/2021/05/pcb-tesla-coil.jpg
https://www.stevehv.4hv.org/SSTC5/miniSSTCfnlsch.JPG
https://www.loneoceans.com/labs/sstc2/sstc2schematicv10.jpg

This leads me to think that there is room for improvement compared to my current layout. Does anything stand out to from the schematics I linked above?
Here is the schematic I am using: except for the 22k resistor.

The loanoceans sstc2 schematic isn't good.  It makes distorted feedback waveforms due to asymmetric clamping directly on the CT output which must average 0Vdc.  Several problematic builds posted on this forum.  Others including what you built are generally fine, with a coupling capacitor between CT and clamp diodes.  If you get to measuring phase, phase lead can be reduced on your circuit by reducing the value of R14 (1k resistor before clamp diodes).  BTW, on all the circuits, it is best to connect unused 74HC14 inputs to 0V or +5V rather than leaving them floating.

I have only been using my scope with my DC supply since I learned the variac was connected to line.

Even with your DC supply, scoping high-side FETs can cause problems.  The DC supply isn't likely directly connected to ground, but does have significant capacitance to ground and/or to AC line.  At 400kHz that capacitance can be somewhat of a short-circuit, or can resonate with scope and DC supply cable inductance to cause artifacts or circuit misbehavior.  Differential scope probes are best for high-side FET scoping.  If not that, a large common-mode choke can help, either in the VBus supply and/or on the scope probe (wind the probe cable around a ferrite E-core and clamp together).  This may or may not be an issue with your setup.

To my surprise there really is not a lot of information out there (at least that I could find on google) about the DC blocking cap for the drive chips/GDT. I just see a lot of "XXuf amount should be good" "no, you need at least XXuf"... You did have an explanation on a thread where you went into detail about using a .1uf cap to power an IGBT full bridge and how it would essentially cause a voltage drop to the overall GDT gate signal voltage since .1uf was too low. That was a helpful explanation.

Yes, it is not a simple subject.  The minimum capacitance is determined by total gate capacitance as in the thread you found.  Damping for the start and end of enable pulses is somewhat more complex.  Some circuits have no additional damping, some (like UD2.7) use another film capacitor with series resistor.  Some (as you found) use electrolytic capacitors with their inherent internal resistance.  Also, large capacitance mitigates the need for damping.  If duty cycle of gate waveforms is very close to 50%, the coupling capacitor can be eliminated.  That is what I typically do.

Is there a good way to use the function generator to induce a signal into the CT (400kHz) so I can mimic when the TC is running? That way I can use my scope to see how the CT signal is processed by the rest of the components. Is it as simple as rapping a few turns around the CT or will the voltage be too low considered the TC secondary voltage is much higher?

Most people feed the driver's CT input with the function generator.  That is what I'd recommend too.  It will be quite helpful to have the function generator.

Hope it goes well!  You are clearly learning a lot from this experimenting.

[ZakW]

The loanoceans sstc2 schematic isn't good.  It makes distorted feedback waveforms due to asymmetric clamping directly on the CT output which must average 0Vdc.  Several problematic builds posted on this forum.  Others including what you built are generally fine, with a coupling capacitor between CT and clamp diodes.  If you get to measuring phase, phase lead can be reduced on your circuit by reducing the value of R14 (1k resistor before clamp diodes).  BTW, on all the circuits, it is best to connect unused 74HC14 inputs to 0V or +5V rather than leaving them floating.

Thanks for confirming that. I also read that in several places as well. I was looking at another thread you posted in regarding the cap and resistor values vs frequency. I will play around more when I get my function generator. All unused inputs are grounded.

As far as phase goes and compensating for the delay, that should be something I can tune and leave alone, right?. The delay I am compensating for by adding/adjusting the phase lead is to correct for any logic delays. I feel like once that is accounted for it should remain constant, is that accurate?

Yes, it is not a simple subject.  The minimum capacitance is determined by total gate capacitance as in the thread you found.  Damping for the start and end of enable pulses is somewhat more complex.  Some circuits have no additional damping, some (like UD2.7) use another film capacitor with series resistor.  Some (as you found) use electrolytic capacitors with their inherent internal resistance.  Also, large capacitance mitigates the need for damping.  If duty cycle of gate waveforms is very close to 50%, the coupling capacitor can be eliminated.  That is what I typically do.

I will take a look at the UD2.7 again to compare, thanks.

If duty cycle of gate waveforms is very close to 50%, the coupling capacitor can be eliminated.  That is what I typically do.

Would a 50% duty cycle at the gate be achieved by a more square output from the GDT rather than the one I am getting, which is more slopped?

Most people feed the driver's CT input with the function generator.  That is what I'd recommend too.  It will be quite helpful to have the function generator.

Sounds good, I am looking forwarding to trying this out. Should be really helpful to see how the signal is processed. I have a feeling the 74hc is not locking onto the correct freq. or it is being disrupted by interference due to incorrect component values.

Hope it goes well!  You are clearly learning a lot from this experimenting.

Thank you! You continued insight and advice is greatly appreciated. Previous builds have not resulted in such multifaceted and compounding problems. But I agree that I have learned a ton in a short time. Enough now to better understand just how complicated this hobby can get.

I will follow up with some tests in a few days or so.

-Zak

[davekni]

As far as phase goes and compensating for the delay, that should be something I can tune and leave alone, right?. The delay I am compensating for by adding/adjusting the phase lead is to correct for any logic delays. I feel like once that is accounted for it should remain constant, is that accurate?

Generally, yes.  Phase can change somewhat with feedback amplitude, but likely not enough to matter.

Would a 50% duty cycle at the gate be achieved by a more square output from the GDT rather than the one I am getting, which is more slopped?

No, duty cycle has little to do with rounding.  It is the fraction of time the gate signal is high.  If high 50% of the time (therefore low 50% of the time), then the average (DC) voltage is zero, so can be connected directly to a GDT.  If not close enough to 50%, then there is too much average DC voltage.  The coupling capacitor removes that DC voltage so that it doesn't cause DC current in the GDT (which could saturate GDT core).

[Rafft]

The coupling capacitor removes that DC voltage so that it doesn't cause DC current in the GDT (which could saturate GDT core).

why does the newer UDs (2.1 upwards) have resistor in parallel with the dc blocking capacitor?

[davekni]

why does the newer UDs (2.1 upwards) have resistor in parallel with the dc blocking capacitor?

The resistor damps the unwanted resonance between GDT inductance and coupling capacitance.  (The unwanted resonance shows up at the start and end of interrupter pulses.)

[Rafft]

why does the newer UDs (2.1 upwards) have resistor in parallel with the dc blocking capacitor?

The resistor damps the unwanted resonance between GDT inductance and coupling capacitance.  (The unwanted resonance shows up at the start and end of interrupter pulses.)

thanks David