Author Topic: Next Gen DRSSTC  (Read 4233 times)

Offline Netzpfuscher

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Re: Next Gen DRSSTC
« Reply #20 on: March 12, 2018, 08:01:52 AM »
I've tried to interpret your scope shot.



It looks like there is a overcurrent event and the driver goes to the freewheeling mode. But I don't know if it should do phaseshift during the ringdown. I haven't tested the QCW mode very much because I have a big low impedance coil. The big mess is under ~90A primary current, what CT ratio did you use?

The input comparator stage has a threshold which is defined in ZCDtoPWM.c:

   //set reference voltage for zero current detector comparators
   ZCDref_Data = 25;

If I find a little bit time, I can do measurements at my coil to see if there are problems with the logic.


« Last Edit: March 12, 2018, 08:04:07 AM by Netzpfuscher »

Offline Hydron

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Re: Next Gen DRSSTC
« Reply #21 on: March 12, 2018, 08:23:55 AM »
Yeah I was thinking about overcurrent, but didn't expect it to do phase shift during ringdown. The threshold is also set to 225A, rather than <150A where it seemed to trip earlier. Later on in the burst it does trip at the correct point, as seen below (QCW modulation finished by this point):


And another with odder behaviour (overall view, part of interest at division labelled 16.05ms):


Zoomed in:


I am still suspicious that there is some element of interference from the hard switching spikes happening here - behaviour seemed better when I'd reduced them by modifying the bridge. Unfortunately I don't think I'm going to have a chance to work on the coil again to test anything until about this time next month, however I will have a go with using the UD3 (and also taking some arc current measurements) on a larger DRSSTC if time permits.

Offline Steve Ward

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Re: Next Gen DRSSTC
« Reply #22 on: March 26, 2018, 03:54:22 AM »
Phase shifting will remain in effect during current limiting, which does tend to make for unusual-looking waveforms as the phase shifted gate signals are still applied alternately between the 2 outputs.  It does appear that there's some phase error in your switching, still, which is a typical side effect of the the current limit function combined with the phase-shift control. The phase-shift bridge switching scheme gives a rise in operating frequency because the driving voltage pulses are leading by a significant phase compared to the primary current.  When it switches to freewheeling/current limit mode, the applied voltage is basically zero, so the phase lead of the driving voltage no longer comes into play, and so the frequency of oscillation will drop.  Toggling quickly between these modes is tricky for the phase predictor thingy and so it misses ZCS by a decent amount under some conditions.  Ideally, your QCW coil is designed so that it does NOT current limit while phase shift modulation is applied.  A few hard switchings should not be a significant problem for a properly designed bridge.

All that being said, did you follow the same schematic as the UD3 for the CT input?  Those filter caps are pretty essential i think... routing long wires to the dev board might be iffy around tesla coils :P.

I used 15 ohm turn on gate resistance with the FGH60N60 IGBTs and i use 2:1 GDT ratio to step the 24V drive to 12V as we are not abusing the peak current rating of the IGBTs in QCW coils.  Be sure you have sufficient dead time in your gate drive to avoid hard commutation of the output voltage.  What i mean is, the IGBT should always switch off early enough so that the primary current causes voltage commutation at the half-bridge output and the IGBT turn on is at zero voltage (ZVS).  If there is not enough deadtime, you will switch the IGBT on before the voltage at the output has changed, and this rapid charging of the other IGBTs junction capacitance can ring at very high frequencies with the stray inductance of your bridge.  Also, if the IGBTs are switching late, and the IGBT turning on must force the opposite diode to recover, this will lead to large spikes as the diode recovery is a high di/dt across the stray inductance.  I observe very nice switching waveforms on the 60n60s even when hard switching in phase shift mode.  Perhaps 50V maximum overshoot with 400V bus and 60A peak current per device.  Going easy on the turn-on seems like a good, simple choice to combat all the downsides of insufficient deadtime or too-hard-reverse-recovery of the co pack diodes giving big voltage spikes.

Offline Netzpfuscher

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Re: Next Gen DRSSTC
« Reply #23 on: May 09, 2018, 12:41:22 PM »
I've made big progress on the UD3 software. The command line now supports more datatypes:

-uint8 / uint16 / uint32
-int8 / int16 / int32
-float
-char
-string

The EEPROM-Dataset is revision save. With the new function it is possible to change the parameterlist and still read the EEPROM to the new parameterlist. The EEPROM function gives a warning if it can't find values in the EEPROM for a new parameter and it warns if there is a value in the EEPROM but not in the firmware.

The next thing I'm working on is a terminal for the UD3. It's based on Chrome App (Javascript) and should run fine on Windows/Linux/Mac. It includes a simple MIDI player which sends the MIDI messages over UART to the UD3 so you don't need a special Interface, a normal USB-UART is fine.

« Last Edit: May 09, 2018, 12:51:54 PM by Netzpfuscher »

Offline profdc9

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Re: Next Gen DRSSTC
« Reply #24 on: May 09, 2018, 05:44:23 PM »
Do you have an example of the interface circuit between the microcontroller UART connection and the MIDI interface? 

Also, I was wondering if it would be possible to connect one of the ESP8266 wireless modules to it and use that for a serial port.  There's a serial to wifi interface here

https://github.com/jeelabs/esp-link

so it would be possible to use Wifi to talk to the terminal rather than USB.  The serial port is totally transparent and as long as there is TTL serial on the microcontroller side you don't need to do anything.  You just have to flash the ESP8266 with this firmware and it becomes a serial to wifi interface with a serial port.  You can get a ESP8266 module on ebay for like $2, and a CH340 to ESP8266 interface for about $1.50.

Thanks,

Dan

Offline Hydron

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Re: Next Gen DRSSTC
« Reply #25 on: May 09, 2018, 06:36:53 PM »
I look forward to playing with the new code! I have been busy/away so haven't had much time to play with the existing stuff other than some more bench tests with my CY8CKIT-059 based QCW prototype (focusing on the power side of stuff rather than software).

profdc9:
As for serial, the command-line interface also comes up on the TTL TX/RX port in exactly the same way as the USB-UART interface, so it would be easy to talk to the ESP8266. The only thing you might need to check is what the UART speed is set to in the cypress design files. I have used this feature to connect via a fibre-optic serial link (see orange wire in post here: https://highvoltageforum.net/index.php?topic=188.msg1778#msg1778 )

Offline Netzpfuscher

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Re: Next Gen DRSSTC
« Reply #26 on: May 09, 2018, 10:28:13 PM »
It should be no problem if you use a transparent WIFI-Bridge. You can send terminal commands and MIDI commands to the TTL-UART on the UD3. The UD3 separates these and route the messages to the MIDI-Interrupter task or to the command line task.

With the new terminal there can be a second option. It is possible to implement a TCP or UDP connection to the ESP8266 over socket. This eliminates the need of a virtual com port driver on the computer side. But the WIFI-Link adds a few ms jitter to the data (MIDI), if the WIFI-Link is weak or there is a lot traffic it sounds a little bit wrong.

Offline Netzpfuscher

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Re: Next Gen DRSSTC
« Reply #27 on: June 17, 2018, 08:35:38 PM »
The first test of teslaterm was a success  :D There is still a lot of work to do and improvements to make, but it's running.

UD3-Firmware with teslaterm support:
https://github.com/Netzpfuscher/UD3_PSOC/tree/new_CLI

Teslaterm:
https://github.com/Netzpfuscher/Teslaterm

For running Teslaterm (drop the folder on the nw.js executable or make a link like this: "C:\nwjs-sdk\nw.exe c:\git\teslaterm"):
https://nwjs.io/


And the demo:

Offline Hydron

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Re: Next Gen DRSSTC
« Reply #28 on: June 18, 2018, 11:46:44 AM »
Ooh, looks very interesting - thanks for the update. I'll let you know when I've had a chance to test it myself.

Offline Mads Barnkob

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Re: Next Gen DRSSTC
« Reply #29 on: June 18, 2018, 01:48:11 PM »
That is a super cool interface and the trend feature is something that can make me order a devkit at once to try this out myself :)

I do however not feel like I have a complete overview of what parts and bits are needed as you all seem to run this on different hardware :o
http://www.kaizerpowerelectronics.dk - Tesla coils, high voltage, pulse power, audio and general electronics

Offline Hydron

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Re: Next Gen DRSSTC
« Reply #30 on: June 18, 2018, 04:27:14 PM »
I'm not so up to speed on the code for the "interface" PCB (seen in first post with LCD), but the UD3 code will run on either of two boards:

1) the UD3 design based on Steve Ward's work and updated by Netzpfuscher (not sure if he's released the files for this publicly). This board comes with primary and secondary CT inputs, USB, UART header, relay/fan control, bus voltage/current monitoring, and GDT driver. No changes necessary to compile/run

2) A PSoC5 dev board, connected to (at a minimum) a CT and external GDT driver. This needs the pinout and device selection of the PSoC project to be changed before compilation, and some support circuitry either on a breadboard (as I did, see pics) or on a support PCB like what profdc9 designed. Ironically the dev board is cheaper than a single PSoC part despite having TWO devices on it (one for the programmer/debugger, which you'll need anyway for bringing up a UD3 PCB).

Both of these boards let you connect via USB (it enumerates as a virtual serial port + USB MIDI controller) or a straight TTL UART connection to the appropriate pins. I believe it falls back to UART if USB is not present, but not 100% sure.
When I used it the PC got very unhappy with EMI when using the chipset-native USB2 controller, but was happy with the motherboard's non-native USB3 controller (operating in USB2 mode). Dunno why one was OK and not the other, but I do know that USB is pretty garbage from an EMC immunity point of view, so you'll probably want to hook up to the serial port via a fibre link for proper full-power testing.
The primary interface via serial port is a command-line (as seen in the video and screenshots); I have not investigated properly what other methods can be used for control as the CLI has worked so far for what I have been testing.

Offline profdc9

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Re: Next Gen DRSSTC
« Reply #31 on: June 18, 2018, 09:07:28 PM »
I built up my PsoC 3 board.  The only things missing are the precision resistors for the voltage bus sensing, and the bus Hall-effect current sensor.  I have tested the microcontroller and verified that it can drive the gates however.   I haven't put it in a coil yet though.  The board for this is in the DRSSTC PCB pack.  The one in there is slightly modified because I moved a few components around to make the USB connector easier to access.



I modified the project for the new pin assignments.  You can get the file in 7zip format below.  It doesn't have any of Netzpfuscher's Tesla term modifications yet though.  I also modified the serial port speed to be 38400 baud rather than 2 Mbaud, because I will probably be using this with either a ESP8266 (which I have used successfully) or with an optical transmitter and receiver.

https://drive.google.com/open?id=19qv76rRRxeaazcwBBeACj1WtnnMVr_3k

One note:  when putting the PSoc5 into the pin socket, you might need to bend the pin sockets in slightly because if they are bowing out, they will tend to push the PSoC5 out of the sockets causing loose connections.  I think this is because it is difficult to get the pin header socket to stand up perfectly straight when soldering it in so you have to tweak it.

I probably won't have time to try this, but I would like to, but I am having too much fun with the UD2.9 skip pulse to take the coil apart, but I will probably try this driver eventually.

Dan
« Last Edit: June 18, 2018, 09:10:28 PM by profdc9 »

Offline Hydron

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Re: Next Gen DRSSTC
« Reply #32 on: June 18, 2018, 11:18:56 PM »
Hah, I was wondering why you were complaining about not having room to fit everything on the PCB, now I understand! (Has been a while since I've done anything with much through-hole stuff on it other than TO-247 half-bridges)

It will run just fine without the sensing stuff (see my minimal breadboard on the first page), just doesn't report anything.

Offline profdc9

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Re: Next Gen DRSSTC
« Reply #33 on: June 19, 2018, 03:19:15 AM »
Yup the PCB is packed.  There's stuff underneath the PSoc5 chip too (low profile resistors and diodes).  Almost every square millimeter is used!

Dan

Offline Netzpfuscher

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Re: Next Gen DRSSTC
« Reply #34 on: June 19, 2018, 08:14:00 AM »
The PCB files are on Github:
https://github.com/Netzpfuscher/UD3_PCB

This design is untested due to a lack of time ^^
I would be very happy if someone helps with the UD3, we need documentation (Git Wiki). A SMD version with Kicad would be a big thing, Altium is to expensive. If we go with the same processor like on the dev-kit (QFN), we only need to maintain one software. I haven't found a good solution in PSOC-Creator to handle more than one processor.

@profdc9
The esp supports way more than 38400 baud. Perhaps the serial bridge software can be modified? If you want to use teslaterm the datarate can be a little bit slow. It works but the terminal can be little bit slow. While a chart/gauge frame is transferred the output of the CLI is blocked, so there can be a delay up to 145ms (70 bytes).  I have a missing option in teslaterm, there is no baud-rate selector :o

Offline Mads Barnkob

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Re: Next Gen DRSSTC
« Reply #35 on: June 20, 2018, 11:26:14 AM »
I would be very happy if someone helps with the UD3, we need documentation (Git Wiki).

I would like to help, but consider me as a completely blank and new guy on that job, I would need a fairly detailed work list :)
http://www.kaizerpowerelectronics.dk - Tesla coils, high voltage, pulse power, audio and general electronics

Offline Netzpfuscher

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Re: Next Gen DRSSTC
« Reply #36 on: June 20, 2018, 02:26:29 PM »
I added a little bit of documentation to the wiki.  8)

https://github.com/Netzpfuscher/UD3_PSOC/wiki

Offline profdc9

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Re: Next Gen DRSSTC
« Reply #37 on: June 20, 2018, 03:15:09 PM »
If it would help you get started with Kicad, I put together a quick SMT board.  However, I used the target board rather than the bare IC because it is difficult to lay out because the target board effectively adds another layer, so I can get away with a two layer board.



Certainly some optimizations could be made.  Most of the footprints are 0805, and there are a handful of components on the back.  The project is attached. There are some things from your design that aren't in mine that could be added (mostly the second current transformer).

Dan

Offline Hydron

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Re: Next Gen DRSSTC
« Reply #38 on: June 20, 2018, 04:08:31 PM »
I am looking at whether PSoC creator supports building for more than one target configuration. It does not look like it's something built in, so may be a case of copying source files between two separate projects (annoying, but doable).

I can also have a look at updating Netzpfuscher's (untested) PCB to use the same pinout, device etc as the dev board, but it may not be that simple on a 2-layer board with a QFN (also requires hot air to solder the chip, vs a QFP which is do-able with a reasonable iron).
« Last Edit: June 20, 2018, 04:11:32 PM by Hydron »

Offline profdc9

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Re: Next Gen DRSSTC
« Reply #39 on: June 20, 2018, 08:14:29 PM »
Would it be possible to just change the same pins so that different parts would be used but the pins would be essentially the same?  There would be some flexibility to changing the pins of the devkit model but of course many pins are committed to things like capacitors, switches, and the two-wire port.

Dan

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Re: Next Gen DRSSTC
« Reply #39 on: June 20, 2018, 08:14:29 PM »

 


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