Author Topic: DRSSTC Design Help?  (Read 774 times)

Offline GKnapp

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DRSSTC Design Help?
« on: December 20, 2020, 03:45:11 PM »
Hey all!

I finally got back to the part of the country with my drsstc, replaced the damaged transistors, got it working for like a minute, and then blew out the transistors. They're a pain to replace, and so I want to make sure I get it right this time. I have some questions, and I hope that you'll be able to help give me advice.

When I first replaced the igbts, sparks were very small, much smaller than before it broke several months ago. Every few bangs I would get a big spark with a nice sounding "thump." Based on some comments that Mads made on a thread, I figured this meant that somehow my feedback was getting messed up. I slid around my top acrylic plate, moving the feedback coils farther away from the primary (only by like half an inch), and I got large sparks. I was fighting against the OCD even with the fastest ontimes (~30 us). I then changed the breakout point to one that was smaller (but had worked previously on the coil) and that was too hard on the coil and the transistors died after a few seconds of weak sparks.

1) I had my OCD set below 300 amps, for FGA65N60 igbts. The physical coil design I was following (Loneoceans drsstc1) was able to successfully have these transistors run at 300 amps, as have many others. My theory is that since my coupling is so high with the helical primary, the ocd simply isn't fast enough to stop switching before the current rises much too high. Should I just abandon the helical coil and make a flat one instead? I know general opinion is that flat ones are better. I liked how big the sparks I got were when this coil was working (~20 inches with a 10 inch secondary, which I was quite proud of for a first drsstc) but I'd also like the coil to keep on working. Am I correct in thinking that if I had looser coupling, the performance might not be as stellar, but the OCD would also be likely to actually protect my transistors?

2) It seemed like the feedback was getting messed up by being too near the primary. I want to move it farther away, but this will mean that I have to have a long wire going from the primary down to the feedback transformer and then back to the bridge. At the moment, the wires are about as short as they can be, which necessitated having the current and feedback coils quite near the primary. Is the tradeoff of a longer primary lead something to worry about in terms of extra inductance, or with a coil of this small size is it not a big deal? If it is a big deal, do you have design suggestions for getting around this interference problem?

I've included several pictures of the overall layout and setup, and if you have any suggestions for changing it so it's more robust or easier to adjust, I'd love to hear them. I'm also thinking about changing the order of the driver and the bridge, though this would mean that I'd have to have the heatsink sticking up, and I'm not quite sure about that. But in general, it's a pain to unscrew everything, then try to desolder four through-hole igbts to replace them (or two of them). Not sure how I could make the replacement process easier other than by using a different bridge design... but these boards came from profdc9's drsstc pack and I quite like them. Thank you for any help or advice you can give!






Offline AstRii

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Re: DRSSTC Design Help?
« Reply #1 on: December 20, 2020, 04:31:31 PM »
There can be many more factors which could blow up the IGBTs. Have you measured the waveforms? Your Gate-drive might be poor, your phase lead might be insufficient or you can have a cross-conduction situation in your bridge.
I think that even in the worst case, OCD is fast enough to trigger. But i would go for a looser coupling anyway, so that you can run higher on-times and lower peak currents (on perfect tune).
30us is pretty quick for 300A current, are you sure your coil was properly tuned?
It's better if your feedback works with a bit of GDT leakage inductance than not working with perfect GDT connection :)
Place the GDT close to the bridge and run GDT primary as 4 parallel twisted wires (one for each secondary), this dramatically reduces the inductance.

Nice job so far, good luck and happy coiling :)

Offline GKnapp

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Re: DRSSTC Design Help?
« Reply #2 on: December 20, 2020, 06:49:13 PM »
Thanks for the response!

I did measure the waveforms, but not recently. They used to look good, and the phase lead seemed to be reducing the spikes, though I had trouble getting it to eliminate them too much.

I'm still mostly a noob--what would cause a cross-conduction situation, and what does that mean?
Good to know that the ocd should work, but worrying if it means that something is more seriously wrong.

Thanks for the tip on the gdt!

Offline davekni

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Re: DRSSTC Design Help?
« Reply #3 on: December 20, 2020, 07:43:49 PM »
I doubt the CT to primary proximity is causing issues, unless primary field is enough to saturate the cores.  You could rotate the CT mounting such that the holes through the cores point towards the center post.  That way windings are orthogonal to primary winding, so a bit less chance of interference.  Also rotate about a horizontal axis so the second-stage cores are below the first-stage ones.  The second-stage is more sensitive, so that way it is farther from the primary.  Dipole field drops as 1/r^3, so a little more separation makes a big difference.  If you do move it farther, twist or tape together the primary lead down to the CT with the one back to the H-Bridge.  The paired primary lead length will add relatively little to inductance.

I also doubt your high coupling is causing OCD issues.  If you need to make primary current ramp up more slowly, increase primary turns and reduce MMC capacitance and increase it's voltage.  (30us to OCD does seem quite fast, so more primary turns might be a good option.)  That will make current ramp up more slowly.  Scope waveforms will show if current is ramping enough each cycle to go from below OCD threshold to damaging in one cycle.  Or calculate or simulate it based on bus voltage and primary inductance and MMC capacitance.

Small sparks sounds like tuning is off.  Scope traces are useful for that too.  Run VBus at low voltage (say <100V) for all the scoping first to avoid more IGBT replacement.

BTW, if you do have issues with your vertical primary winding, it will likely be arcing along the lower part of the secondary due to high local field.

Good luck!
« Last Edit: December 20, 2020, 08:22:21 PM by davekni »
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Offline Mads Barnkob

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Re: DRSSTC Design Help?
« Reply #4 on: December 20, 2020, 09:07:30 PM »
Seems you have already gotten a good deal of advise and things to try out.

One thing I noticed that was not mentioned yet, you have placed your current transformers between the primary coil and resonant capacitor. The voltage between the L and C is much higher here than at any of the ends connected directly to one of the inverter outputs. This should not be your issue unless you can find signs of flash-over on the CTs.

What is your coupling at? With no tap'able primary coil, how did you tune it? You are properly running it way out of tune and hitting a high primary current due to missing frequency track.
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Offline AstRii

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Re: DRSSTC Design Help?
« Reply #5 on: December 21, 2020, 12:35:19 AM »
what would cause a cross-conduction situation, and what does that mean?

A cross conduction is a state during which all the IGBTs are partially on which creates a momentary short circuit. This can happen if you use gate-drive with 50% duty cycle.
This problem is usually solved by placing resistor in series with the gate of the IGBT to charge the gate slower, and also placing anti parallel diode to the resistor so the gate can discharge much faster through the diode.
This is usually enough to solve cross-conduction scenarios.

Offline GKnapp

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Re: DRSSTC Design Help?
« Reply #6 on: December 21, 2020, 02:06:19 AM »
Thank you all for the good suggestions!

I'm reasonably sure that the tuning is correct. I had this same coil working well with around 7.75 primary turns a few months ago, which was about a 20% detune of the primary according to Javatc. This time around, in an attempt to not have igbts fail, I reduced the primary turns to more like 7.6 ish in the hope that without the primary frequency as far below the secondary, I wouldn't need as much streamer loading before it was in tune.

I haven't seen anything like flashover, but I think I'm going to need to change the whole layout anyways if I go to a flat or conical primary. Or maybe I'll change the primary to a helical one that is tappable, though before i had secondary racing sparks when the coil reached any higher up the side of the secondary...

The bridge board I'm using has gate resistors and diodes, and I haven't changed anything about the electronics since this coil was last working semi reliably, so it's hard for me to imagine that I would have cross conduction issues--but if you say that the OCD should be protecting stuff then obviously something is seriously wrong.

Maybe I'll try changing which leg of the bridge the CTs are on and orienting them downward as suggested, and see where that gets me. I really think that feedback must be part of the problem, because I don't see what else would explain the dramatic difference in spark length from my slightly shifting the primary and secondary top plate.

Offline GKnapp

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Re: DRSSTC Design Help?
« Reply #7 on: December 27, 2020, 09:24:55 PM »
I replaced the transistors and changed the primary to one that's flat and has less coupling, and changed which leg the CTs are on. I'm going very slowly to make sure that everything is correct. So far so good, and it's switching, but the waveforms are very humped. This is the G-E voltage, switching about 8 volts (minimum that I need for the feedback kick in) and no secondary. Sorry it's blurry, not sure why that is.



I assume this shape could be a lethal threat to the transistors, especially with 170 volts instead of 8. I would like them to look much more square. Is this a problem with too little gate resistance (I currently have 5.1ohm resistors on the gates) or with extra inductance somewhere? Someone on a facebook group suggested that my GDT could be the issue--I've attached an image of that too, as well as one of my new primary. Should I try increasing the value of the gate resistors, somehow redoing the gdt, or are there other things I haven't thought of that could be causing such poor switching? Thank you all for your help and suggestions!





Offline davekni

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Re: DRSSTC Design Help?
« Reply #8 on: December 28, 2020, 12:28:18 AM »
Your GDT is likely fine.  There is some risk with using enamel-insulated wire, especially the normal single-layer-coated type.  The enamel isn't designed to support hundreds of volts and is easily scratched.  If you do rewind with thicker insulation wire, I suggest using four twisted pairs with one half of each pair connected in parallel as the primary.

You said the scope trace was of Vge.  That won't ever be 170V.  Ignoring spikes, the waveform shown is about +-3V.  Or, is it really +-30V with a 10x probe?  (BTW, I suggest changing vertical mode to DC-coupled.  It is harder to interpret waveforms when any DC component has been removed.)

The flat primary has more turns closer to your drive circuitry.  Hopefully that still won't cause any issues.
David Knierim

Offline GKnapp

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Re: DRSSTC Design Help?
« Reply #9 on: December 28, 2020, 05:46:48 PM »
If I do change the gdt I'll use cat5 wires and follow your suggestion.

My bad on the voltage--after having a read through of Steve Ward's waveform testing paper (https://kaizerpowerelectronics.dk/files/application_notes/tesla_coil/drsstc_testing_and_verification_paper.pdf)
I thought that maybe that humpy shape was just that I hadn't adequately twisted the wires on the oscilloscope probe. Still not sure if this is the case or not--if so I can't get the leads close enough to stop it. Just in case, I upped the gate resistance to 10 ohms.

Today, after getting the phasing of everything right, I did some testing at 60vdc and less, and came up with some questions and answers. The OCD still kicked in at around 35 us, but it wasn't consistent, and some tunings caused it to not turn on at all (at least at 60 volts). The OCD wasn't consistent, but it was repetitive, and I checked out my interrupter and found a weird repeating pattern of every few pulses it would make a pulse that was slightly longer. I'm not sure how much that matters--Here's a picture of the usual length overlayed on the extended length. To me it seems like a small percentage, but maybe it has some weird effect on the coil?



Hopefully you all can help me with my tuning strategy. With my new primary I gave myself from 5.8-6.75 ish turns of tappable wire, which Javatc thinks is about 5%-22% lower than the secondary (230khz), depending on tap location. When I'm too far out of tune, the voltage isn't big enough to break out from a small point, and if it does the ocd trips almost immediately. As for tuning, should I

1) put the size breakout point that i would like it to run with, and find a location where sparks break most easily and the ocd doesn't trip?

2) put an extra-long breakout point to simulate the size of streamer I would like it to have at full power, and tap it where it makes sparks most easily? My theory being that since streamers lower the secondary frequency, I actually want to tune for the streamer at full size, not little fuzzy corona at a lower voltage.

However, with my extra-twitchy ocd, I'm not sure how effective (2) will be. I still don't know why the ocd is so happy to turn on--with my new primary, the coupling is lower at around .13 or so. Do you think it could be something weird with the interrupter? Any advice on further troubleshooting is very welcome.

So far, I didn't notice my potential original feedback problem, though when I did move the secondary/primary plate off center, the ocd kicked in even at pretty low voltages.

Here's a picture of the new Vge and Vce traces, with DC coupling like you said. They don't look great to me. First picture is gate, next is the c-e voltage. The weird spike is where the interrupt signal stops I assume. Are these usable? If they aren't, what should my next steps be, to either clean up the waveforms or figure out why the OCD is so fast to turn on?



Offline davekni

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Re: DRSSTC Design Help?
« Reply #10 on: December 28, 2020, 09:20:39 PM »
Yes, 10 ohms should be better for dead time.  Still only ~60ns for those FGA65N60 IGBTs with ~6nF total input capacitance.  They are fast IGBTs.  60ns is likely enough.  My last TO247 H-Bridge uses 33 ohms for pairs of TO247 IGBTs to get ~300ns dead time, enough for slower IGBTs.  Even with your fast IGBTs, I don't think 20 ohms would do any harm, and might filter out that overshoot at the end of enable.

What voltage are you sending your (UD2.7?) driver?  Vge looks to be about +-28V after overshoot settles.  I'd suggest no more than +-24V nominal to keep peaks under +-30V.  Mostly the Vge waveform looks fine.  There is a short overshoot pulse at the end of enable that goes high enough to be the likely cause of the Vce spike.  I've seen this on other threads too.  May be due to delay of the HC74 chip allowing a brief driver transition before disable.  If parasitic inductance is low enough on VBus from IGBTs to snubber caps, the spike may be fine.  Such Vce spikes often don't scale with VBus.  If it does scale, that 2x Vce spike will be a problem.

The Vce hump after the turn-off spike is caused by inductance between local VBus snubber caps and bulk VBus capacitance.  Amplitude of that hump scales with primary current.  As long as the trace was taken with at least 10% of max primary current, then the ~20V hump will scale to no more than 200V, so stay within IGBT voltage limits even at 325Vbus.

There is an unusual ring two cycles after the Vce turn-off hump, just before the final normal ring-down caused by IGBT capacitance and primary inductance.  I doubt it is problematic, but can't explain why it would be there.

Is your interrupter in the same array of boards as the driver and H-Bridge?  If so, the interrupter may be getting confused with stray fields.  Most interrupters are kept well away from the coil, connected only by the fiber cable.

Can you scope primary current (ie. the voltage across the 51-ohm burden resistor in the UD2.7 feedback input circuit)?  That will show if OCD is tripping to do real current or some glitch.  If OCD is tripping early, then scoping the OCD inputs will help too.

It's hard to tell without zooming in to Vce edges, but a bit more phase-lead might be helpful (higher L1 adjustment in the driver).

Yes, I'd figure out OCD issues before fine tuning.  In general, I'd tune close to resonance first (your option 1).  Then, after everything is working well, lower the primary frequency (increase inductance) a bit with your option 2.
David Knierim

Offline GKnapp

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Re: DRSSTC Design Help?
« Reply #11 on: December 29, 2020, 05:20:16 PM »
Hi Dave,
 
Yes it's a ud2.7.
In theory I have a dedicated 24 volt supply for it--voltage measured was 24.8v... Interrupter is isolated and has a fiber going to the driver board. It's small--about 4 feet, but I should think that would be enough to avoid interference for testing at <60 volts...

Also, it's a full bridge and it's max planned voltage is 170 Vbus. When I had this coil working months ago, it had great output at almost 20 inches, so I'm not aiming for more than that.

That said, I can't do much more because my interrupter suddenly started malfunctioning. It's a pretty shoddy affair, but it's also dead simple as it's an attiny85 and two pots and pretty much nothing else. But for some reason now it only has a constant frequency. Before I noticed this, I did get this picture of the voltage across the burden resistor of the OCD--but I don't know what I should be looking for here to tell what's really happening, and during the course of testing the OCD didn't trigger. I also stopped testing because the interrupter wasn't behaving and I didn't want to do any damage. This looks horribly messy--is this normal? I had the leads to the probe twisted together and such, so hopefully it's not just noise.



Guess I have to remake the interrupter before I can do any more testing, and maybe redoing it will get rid of its gremlins! I'd feel pretty silly but also relieved if all my problems were interrupter-related.

Offline davekni

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Re: DRSSTC Design Help?
« Reply #12 on: December 29, 2020, 09:07:19 PM »
Wat turns ratios are your CTs?  The OCD burden resistor plot must be all noise, or else the diode bridge is fried.  It should be positive voltage only.  It is also quite low amplitude.  If your CTs have a total ratio of 1000:1, then 300A would be 0.3A into 2.55 ohms for 0.765V.

4 feet should be enough if the interrupter is 4 feet from the coil.  If the interrupter is close, with 4 feet of looped cable, it could still be a problem.  Good luck with fixing the interrupter.

The measured +-28Vge could be caused by a scope probe that needs tweaking.  The high-frequency compensation adjustment on the probe (to match scope input capacitance) causes undershoot or overshoot on a 1kHz square wave.  At 200kHz, it behaves more as just a gain error.
David Knierim

Offline GKnapp

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Re: DRSSTC Design Help?
« Reply #13 on: December 29, 2020, 10:23:42 PM »
Both the OCD and Feedback CTs are 289:1 (17 turns each). So since I was aiming for <~300 amps peak, 300/289= 1.038*5.1 ohm burden = about 5.3 volts, and I have the OCD pot set for like 5.25 volts to be conservative.

I'll definitely check the diodes--that sounds like something concrete to check! And I'm pretty sure I was being careful to keep the interrupter away, but maybe I wasn't careful enough. Thank you again. Now that you mention it it makes no sense for it to be dipping down into the negative.

Offline davekni

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Re: DRSSTC Design Help?
« Reply #14 on: December 30, 2020, 12:34:29 AM »
The tiny signal on OCD burden resistor is likely noise given 289:1 CT.  Do you have only one of the 5.1-ohm resistors populated?  Presuming so, then that ~0.1V signal would correlate to only 289 * 0.1 / 5.1 = 5.7A primary current.  Or, shorted diodes could be causing the low signal.
David Knierim

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Re: DRSSTC Design Help?
« Reply #14 on: December 30, 2020, 12:34:29 AM »

 


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post Re: Large coil experimenting with long on-times.
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
February 25, 2021, 08:37:26 PM
post Re: Large coil experimenting with long on-times.
[Dual Resonant Solid State Tesla coils (DRSSTC)]
fh89
February 25, 2021, 08:29:10 PM
post Re: Very old flyback
[Transformer (Ferrite Core)]
davekni
February 25, 2021, 07:54:08 PM
post Re: Large coil experimenting with long on-times.
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
February 25, 2021, 06:49:00 PM
post Re: Large coil experimenting with long on-times.
[Dual Resonant Solid State Tesla coils (DRSSTC)]
fh89
February 25, 2021, 06:01:13 PM
post Re: Try to make a full Bridge with IGBT and GDT
[Dual Resonant Solid State Tesla coils (DRSSTC)]
JCF
February 25, 2021, 04:49:19 PM

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