Author Topic: PLL SSTC oscilloscope measurements  (Read 955 times)

Offline davekni

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Re: PLL SSTC oscilloscope measurements
« Reply #20 on: December 15, 2020, 10:07:15 PM »
Thank you for sharing pictures, and for the link to the design the SSTC-III design that inspired you!  That SSTC-III design looks to have high coupling.  Still surprising to me that ZCS operation is possible with large arcs.  I noticed one detail in the SSTC-III design that I wouldn't recommend, although it is obviously working:

Notice that GDT primary leads pass through different slots in the steel case.  That is adding parasitic inductance.  Ideally the GDT wires remain paired (ie. twisted) for their entire length.

Do you have specifications for your GDT core?  That yellow color reminds me of typical powder-iron cores.  Parasitic inductance will be reduced if you use fewer turns on a good ferrite core, such as the four-turn GDT in the SSTC-III example.  It is even better to wind the GDT with four twisted pairs.  One wire of each pair is for secondaries.  The other four wires, one from each pair, are in parallel for the primary.

Another nice feature of the referenced SSTC-III design is that the H-Bridge heat-sink forms a ground-plane immediately under the power ECB traces.  That reduces parasitic inductance.  You could get some reduction by adding copper tape (or aluminum sheet or etc.) to the bottom side of your power ECB, ideally extending to the heat-sinks.  Even better is to implement the H-Bridge power wiring as copper planes as in this example layout I made:
https://highvoltageforum.net/index.php?topic=1324.msg9886#msg9886
David Knierim

Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #21 on: December 16, 2020, 12:12:52 AM »
Thank you for sharing pictures, and for the link to the design the SSTC-III design that inspired you!  That SSTC-III design looks to have high coupling.  Still surprising to me that ZCS operation is possible with large arcs.  I noticed one detail in the SSTC-III design that I wouldn't recommend, although it is obviously working:

Notice that GDT primary leads pass through different slots in the steel case.  That is adding parasitic inductance.  Ideally the GDT wires remain paired (ie. twisted) for their entire length.

Do you have specifications for your GDT core?  That yellow color reminds me of typical powder-iron cores.  Parasitic inductance will be reduced if you use fewer turns on a good ferrite core, such as the four-turn GDT in the SSTC-III example.  It is even better to wind the GDT with four twisted pairs.  One wire of each pair is for secondaries.  The other four wires, one from each pair, are in parallel for the primary.

Another nice feature of the referenced SSTC-III design is that the H-Bridge heat-sink forms a ground-plane immediately under the power ECB traces.  That reduces parasitic inductance.  You could get some reduction by adding copper tape (or aluminum sheet or etc.) to the bottom side of your power ECB, ideally extending to the heat-sinks.  Even better is to implement the H-Bridge power wiring as copper planes as in this example layout I made:
https://highvoltageforum.net/index.php?topic=1324.msg9886#msg9886

My GDT wires are twisted for their entire lenght. But that is interesting, I didn´t notice that and I have read the site more than 10 times.

Yeah, I have specifications. It is this core: https://www.tme.eu/cz/en/details/tx42_26-3e25/ring-ferrites/ferroxcube/tx42-26-13-3e25/
Before I bought this one I used random core from microwave oven input filter and it works very well, but the problem was, that it is small and I can´t use it for full bridge.
Ok, that looks very interesting for me. I will probably rewind my GDT. It is good looking square wave, but it has some spikes and they are much bigger than my previous GDT. This GDT was wound up just by twisting 5 wires together. It has 16 turn on secondaries and 13 turn on primary, so it step up my 13,7V from UCCs to about 18V.
And one quick question. Is it ok to use solid core wire or is it better to use stranded wire? Right now I am using solid core...

Thank you for sending me your article. I will read it as soon as possible. I have some aluminium tape left, so I can use it.

And thank you very much for replying me. I really appreciate it.
« Last Edit: December 16, 2020, 12:34:50 AM by Rapy2 »

Offline davekni

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Re: PLL SSTC oscilloscope measurements
« Reply #22 on: December 16, 2020, 04:15:53 AM »
That GDT core is fine.  Turn ratios other than 1:1 make low leakage inductance difficult.  Most drivers for IGBTs such as UD2.7 (for DRSSTC) us discrete FETs after the driver chips to boost gate voltage to +-24V before the GDT.  There are some driver chips capable of more voltage too.  However, reasonable leakage inductance may be possible with fewer turns, perhaps 4:5.

That core lists cross-sectional area of 95.8mm^2.  Using 0.22T saturation to be conservative (spec. at 100C), that is 95.8mm^2 * 0.22T = 21uVs per turn.  Per your scope plot, a half-cycle on your coil is 2.1us wide.  Thus you can run up to 10V/turn on the GDT before saturation (21uVs/turn / 2.1us = 10V).  So a 4-turn primary and 5-turn secondary would have plenty of margin away from saturation.  You could wind 4 turns with twisted pairs, then add one more turn for each secondary back over the top of the initial four turns to minimize spacing and therefore minimize leakage inductance.  Then parallel the four primary wires.  Best is to keep each of the four primary winding leads twisted with themselves back to the driver, connecting them in parallel at the driver.  That way the lead inductance is cut by a factor of 4.  Solid or stranded makes no difference.
David Knierim

Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #23 on: December 16, 2020, 11:08:57 AM »
That GDT core is fine.  Turn ratios other than 1:1 make low leakage inductance difficult.  Most drivers for IGBTs such as UD2.7 (for DRSSTC) us discrete FETs after the driver chips to boost gate voltage to +-24V before the GDT.  There are some driver chips capable of more voltage too.  However, reasonable leakage inductance may be possible with fewer turns, perhaps 4:5.

That core lists cross-sectional area of 95.8mm^2.  Using 0.22T saturation to be conservative (spec. at 100C), that is 95.8mm^2 * 0.22T = 21uVs per turn.  Per your scope plot, a half-cycle on your coil is 2.1us wide.  Thus you can run up to 10V/turn on the GDT before saturation (21uVs/turn / 2.1us = 10V).  So a 4-turn primary and 5-turn secondary would have plenty of margin away from saturation.  You could wind 4 turns with twisted pairs, then add one more turn for each secondary back over the top of the initial four turns to minimize spacing and therefore minimize leakage inductance.  Then parallel the four primary wires.  Best is to keep each of the four primary winding leads twisted with themselves back to the driver, connecting them in parallel at the driver.  That way the lead inductance is cut by a factor of 4.  Solid or stranded makes no difference.

Ok, thank you very much. I will rewind my GDT with just 4:5 wires and hopefully it will decrease voltage spikes.

Offline davekni

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Re: PLL SSTC oscilloscope measurements
« Reply #24 on: December 16, 2020, 07:35:18 PM »
Please check gate waveforms with your scope after rewinding the GDT.  I don't expect the UCC37321/2 chips to have trouble with the roughly +-0.15A magnetization current.  Still good to check before running at high power.  All my experience has been with FETs driving GDTs such as in UD2.7 driver schematics.  I have no personal experience with driver chips connected directly to a GDT.

A bit more explanation:  A 4-turn primary on your GDT core is far below saturation as I posted previously.  The lower turn-count also reduces inductance, which increases current.  The core lists 6.4uH/turn^2, so 16 * 6.4 = 102uH for 4 turns.  That results in about +-0.15A current at your 240kHz frequency.  With FETs driving GDTs, even 1 or 2A isn't problematic.  I think +-0.15A will be fine directly from the driver chips.  Check to make sure.

BTW, when your IGBTs have failed in the past, did the external diodes you have across them also fail?  If so, it is possible that a diode failed first and then the failed (shorted) diode caused IGBTs to fail.
« Last Edit: December 16, 2020, 07:38:38 PM by davekni »
David Knierim

Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #25 on: December 16, 2020, 11:27:01 PM »
Please check gate waveforms with your scope after rewinding the GDT.  I don't expect the UCC37321/2 chips to have trouble with the roughly +-0.15A magnetization current.  Still good to check before running at high power.  All my experience has been with FETs driving GDTs such as in UD2.7 driver schematics.  I have no personal experience with driver chips connected directly to a GDT.

A bit more explanation:  A 4-turn primary on your GDT core is far below saturation as I posted previously.  The lower turn-count also reduces inductance, which increases current.  The core lists 6.4uH/turn^2, so 16 * 6.4 = 102uH for 4 turns.  That results in about +-0.15A current at your 240kHz frequency.  With FETs driving GDTs, even 1 or 2A isn't problematic.  I think +-0.15A will be fine directly from the driver chips.  Check to make sure.

BTW, when your IGBTs have failed in the past, did the external diodes you have across them also fail?  If so, it is possible that a diode failed first and then the failed (shorted) diode caused IGBTs to fail.
Thanks for explanation. I will check my gate waveforms on scope. My experience is that this chips works well and I never had a problem. Single UCC chip can output 0.6A current and +-9A peak current. I have 4 chips, every 2 in parallel, so it shouldn´t be a problem. I have read about FETs driving GDT, but this chips work for this medium SSTC well and I want to keep it simple and small.

When my IGBTs have failed in the past, the external diodes didn´t fail. I have MUR1560 across them, but I think, that they are slower than the internal diode in this IGBT (FGA60N65SMD), because when it was running, this external diodes never got even warm, so I think that they were there just for decoration... According to the datasheets, internal diodes have 47ns trr and external 60ns trr, so it looks like I said before.

 

Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #26 on: December 16, 2020, 11:51:45 PM »
And back to ZCS. I am attaching a photo of waveforms on my old setup. It is like month ago. It was just a halfbridge and I tried to set up the phase to ZCS. In the picture it is running at full power. Althought the waveforms look good, it is not switching at peaks, the halfbridge always blew up after a few seconds. So I decided to build full bridge, but there is same problem and it is not even possible to set this waveforms, it is switching at peaks.

Offline davekni

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Re: PLL SSTC oscilloscope measurements
« Reply #27 on: December 17, 2020, 12:43:34 AM »
The key difference with half-bridge SSTC is the capacitors that that substitute for the other missing half of a full-bridge.  Those capacitors shift phase of the current waveform earlier, making it closer to ZCS.  You can get the same result by adding capacitor(s) in series with the primary coil with full-bridge drive.  If you do that, just be sure capacitance is large enough that primary resonance frequency is well below secondary resonance frequency.  Otherwise you will end up with an unintentional DRSSTC.  With a DRSSTC, primary current limiting circuitry is critical.

A couple people here have added schottky diodes (1N5819 or 1N5818 or ...) from driver chip outputs to driver chip +15V supply.  There's concern that the negative part of the GDT magnetization current (after switching) can cause UCC2732x outputs to go enough above their supply rail to fry driver chips.  It certainly wouldn't do any harm to add those two schottky diodes if you have any similar parts around.  A single diode will suffice for two paralleled driver chips, so only two diodes total are needed.
« Last Edit: December 17, 2020, 02:04:28 AM by davekni »
David Knierim

Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #28 on: December 17, 2020, 08:18:08 AM »
The key difference with half-bridge SSTC is the capacitors that that substitute for the other missing half of a full-bridge.  Those capacitors shift phase of the current waveform earlier, making it closer to ZCS.  You can get the same result by adding capacitor(s) in series with the primary coil with full-bridge drive.  If you do that, just be sure capacitance is large enough that primary resonance frequency is well below secondary resonance frequency.  Otherwise you will end up with an unintentional DRSSTC.  With a DRSSTC, primary current limiting circuitry is critical.

A couple people here have added schottky diodes (1N5819 or 1N5818 or ...) from driver chip outputs to driver chip +15V supply.  There's concern that the negative part of the GDT magnetization current (after switching) can cause UCC2732x outputs to go enough above their supply rail to fry driver chips.  It certainly wouldn't do any harm to add those two schottky diodes if you have any similar parts around.  A single diode will suffice for two paralleled driver chips, so only two diodes total are needed.
Yeah, I had this capacitor in series with primary for DC blocking task. I calculated it, so my primary resonance was about 25k, so it was ok and cannot accidentally work as DRSSTC. I will add it here too.

I don't have this diodes here. I will add them. Maybe it will reduce chips heating. Thank you!

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Re: PLL SSTC oscilloscope measurements
« Reply #28 on: December 17, 2020, 08:18:08 AM »

 


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