Author Topic: Steve wards UD1.3 driver understanding help  (Read 325 times)

Offline prabhatkumar

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Steve wards UD1.3 driver understanding help
« on: June 22, 2020, 08:49:54 PM »
Hello everyone !! I was just learning about all the logic which is involved in a DRSSTC as compared to SSTC. I could understand the flip flop ( for the ZCS) easily but from a different source( Lone oceans SSTC3 had explained it well ). So now I wanted to understand how to the OCD works even though I wont e using that in a SSTC anyways, but it is still good to know I think as someday I might even plan to upgrade to a DRSSTC.
Now first things first. I am not very experienced when it comes to electronics. Just will start with analog electronics in this semester but I have some very basic understanding. I have decent knowledge of the digital electronics part since it was there in my semester earlier.
Schematic for the UD1.3( attached is screenshot of the same).


So I started wandering around for some explanation of the driver but failed to find it. I stumbled across the Ud1.3 which is used with some changes at many places like lone oceans SSTC4(If I am correct). So here goes my list of questions( Please excuse if they are dumb questions):
1) After the IC2A(74hc08), why is that we need to invert the signal twice and feed the output of each state to the PRE' and CLR' inputs? I know there will be some good brains involved there, but if someone is kind enough to explain by a simple table or a few lines, please do it. Also why is the diode (D7)and resistor(R2) there at the output of IC1A(74hc14). What purpose it is serving there?
I have couple of questions from the UD2.1 as well but that will come after this one is answered.
Thank you !!

Offline Mads Barnkob

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Re: Steve wards UD1.3 driver understanding help
« Reply #1 on: June 22, 2020, 09:01:45 PM »
The inverters after IC2A is there because the inputs of IC3A are NOT.

It can also be a result of the experiments of Steve Ward to make the driver behave as he wanted, he did a lot of development with circuit timings, so adding in inverting gates could in some cases be for timing purposes.

D7 / R2 on IC1A is again a timing thing, fast turn-on and slow turn-off, or vise-versa
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Offline prabhatkumar

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Re: Steve wards UD1.3 driver understanding help
« Reply #2 on: June 22, 2020, 09:32:54 PM »
Thanks for the quick reply !! I understood about the diode and resistor used there now.
One thing, If I have understood it right then the output of the interrupter is already inverted once then fed to the flip flop. what I am not sure about is that whether the outputs from the fibre optic used here is active low or not . If active low then the inverter directly at the output of the interrupter signal makes sense. Otherwise that would be for giving the desired result on the flip flop output . Please correct me if I am wrong

Offline davekni

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Re: Steve wards UD1.3 driver understanding help
« Reply #3 on: June 22, 2020, 09:49:20 PM »
At the start of an enable pulse, IC1A output goes low, presetting IC3A high to enable oscillation.  D7 rapidly discharges C3, making IC1B output high, removing clear from IC3A.

When either OCD trips or the enable pulse ends, IC1A output goes high, removing preset from IC3A.  The next rising edge from IC1D (CT feedback) clocks IC3A output low (since its D input is tied low).  This terminates gate drive at a current zero-crossing, which is the preferred time to avoid IGBT stress.

If, however, some fault has caused oscillation to stop, there will be no rising edges on IC1D.  In this case, after ~400us, C3 charges sufficiently to make IC1B output go low, clearing IC3A.  Think of this as the emergency-shutoff.  In a failure situation where oscillation stops for 400us, this will make sure that gate-drive is still stopped.
David Knierim

Offline Mads Barnkob

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Re: Steve wards UD1.3 driver understanding help
« Reply #4 on: June 22, 2020, 11:23:47 PM »
Thanks for the quick reply !! I understood about the diode and resistor used there now.
One thing, If I have understood it right then the output of the interrupter is already inverted once then fed to the flip flop. what I am not sure about is that whether the outputs from the fibre optic used here is active low or not . If active low then the inverter directly at the output of the interrupter signal makes sense. Otherwise that would be for giving the desired result on the flip flop output . Please correct me if I am wrong

You are right about IC1F being there to change phase of the optic receiver.

Steve Ward used a inverting type and I actually used a non-inverting type, so I have IC1F bridged over and the legs lifted from the socket in my drivers :)
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Offline prabhatkumar

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Re: Steve wards UD1.3 driver understanding help
« Reply #5 on: June 23, 2020, 05:38:43 AM »
Thank you davekni for the wonderful explanation !! Really the brains which Steve ward has put here is great. Also mads thanks for the reciever doubt clarification.
Regarding the no pulse detection for ~400us, can I tweak the resistor and capacitor values for getting a higher on time here . This is because I will be using a SSTC and I could get around 1.5 ms I think without killing anything( I hope so ).I will be using optocoupler instead of the optical reciever. I have 4n35 and pc817 opto couplers. Which one would be better to use here ? . I will place my interruppter directly on the main board itself using some headers like lone oceans did
EDIT:
I am again getting confused over the operation. I will try to explain whatever I have understood from here. When there is no OCD, then the output of the IC2A would be the same as the interupter pulse. I assume here that when the interupter outputs 1 and that means drive on( LOGIC HIGH). So when the interrupter gives LOGIC 1, then PRE'  is pulled low and hence drive turns on. The capacitor C3 remains discharged, and hence CLR' is pulled high, basically just making the CLR' ineffective. Now if the CLK ( primary current is still high) , while the interrupter give a low pulse then PRE' is pulled high while the capacitor starts charging and takes around 400uS to reach the threshold for the IC1B. Till then, the if the primary current (if time period is less than 400uS), has a rising edge again and then effectively puts the output low . This achives the ZCS. If for some reason the primary current feedback is disturbed or something has collapsed, then CLR' is pulled to logic zero, effectively shutting the system down. The diode keeps discharging the capacitor faster than the next system clock arrives ( primary current ) .
Also when an OCD event occurs, the PRE' of the IC3A would be 1 and after 400 uS, the CLR' would become 0 forcing the drive to shut down. But during these 400uS wouldn't the FETs or IGBTs get destroyed? I think 400uS is enough to kill a FET given that the junction temperature usually reaches it's maximum in around 20 uS.
« Last Edit: June 23, 2020, 12:27:52 PM by prabhatkumar »

Offline davekni

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Re: Steve wards UD1.3 driver understanding help
« Reply #6 on: June 24, 2020, 04:55:54 AM »
The 400us time-out occurs only if there is a gap in oscillation for that long.  It does not limit normal on-time nor off-time.  (Last year I added a similar function to my interrupter, except that it shuts down when there's a gap in oscillation even if enable is still true and OCD is false.  Time is ~20us, as my oscillation is 80kHz.)  Yes, changing C3 or R2 will change that time.  I'd suggest making it shorter.  Doesn't matter unless there's a serious fault, however, such as an MMC-shorted failure.

In the idle state between enable pulses, C3 is charged.  The diode discharges it quickly at the beginning of enable pulses.  C3 doesn't "remain discharged", but rather is discharged by the diode at the start.  The rest of your explanation is accurate except for the final sentence.  Again, C3 isn't discharged until the next enable pulse.

For your final paragraph about OCD, it shuts down at the next rising zero-current edge, not waiting 400us.  Behaves the same as if the enable pulse ended.  400us applies only if oscillation has stopped (ie. shorted MMC or other such hard failure).  In normal operation, primary current is rising only 10 or 20% each cycle.  Thus waiting for the next rising edge after OCD exposes the H-Bridge IGBTs to only 10-20% more current than the OCD trip point.  OCD should be set a little under the IGBT's max capability for that reason.  (My DRSSTC OCD shuts down on the next zero-current edge, either rising or falling, reducing the amount of additional current.)
David Knierim

Offline prabhatkumar

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Re: Steve wards UD1.3 driver understanding help
« Reply #7 on: June 24, 2020, 08:14:19 AM »
Thank you davekni !! Now I have understood all the working behind the driver and also cleared my confusion about the long OCD trip time.
Now I will be working on a new schematic which will omit the the OCD part as I don't think it's required in a SSTC.  What I wanted to know is that can I do antennae feedback instead of current feedback. And even if I did current feedback, then primary current or secondary current feedback ? Please tell me the possible options for me.

Offline davekni

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Re: Steve wards UD1.3 driver understanding help
« Reply #8 on: June 24, 2020, 10:14:33 PM »
SSTCs use either secondary current or antenna feedback.  DRSSTCs use primary current feedback.
David Knierim

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Re: Steve wards UD1.3 driver understanding help
« Reply #8 on: June 24, 2020, 10:14:33 PM »

 


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