Author Topic: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP  (Read 1751 times)

Offline prabhatkumar

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SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« on: June 06, 2020, 10:10:59 AM »
Hello all !! This post is a followup to my earlier post where I had reported non functional enable pins of the UCC327321 and UCC3322. Now after getting workaround with logic ICs ( AND GATE AND INVERTERS), I have made the requisite changes and then made some tests. I have few doubts on how things should be and what i am getting practically on the oscilloscope. Post from where this started
https://highvoltageforum.net/index.php?topic=997.msg6869#msg6869
suggested fix i tried
https://highvoltageforum.net/index.php?topic=1034.0
The schematic if you dont have time to read all this :
1) I have followed the Kaizer SSTC3 schematics and used the same board with a few changes ( Adding more filtering near the UCCs and also some diodes on the output of the driver ICs to prevent latch up. In the scheme the input from the antennae gets fed to the schmitt trigger( I use CD40106 instead of 74hc14). Then the output of the first schmitt trigger is fed into another to effectively get a nice square wave of the resonant frequency. Now what I have a doubt in is that at the input of the first schmitt trigger , the voltage there is a 1.1 volt approx, which I think is due to the fact that the voltage is clamped by the two germanium diodes(1n60) even though the bridge side of the driver is not powered. Due to this the schmitt trigger treats it as high level and hence after inverting we get around 0 volts at the output of the first schmitt trigger. Now this signal is sent tot eh second schmitt trigger and it outputs a continuous logic high( as input is logic low). This is the signal which is fed to the first and gate along with the interrupter signal. Now whenever the interrupter is on the and gate output is also high. This is sent to one the UCC now according to the scheme. Please tell if i need to directly connect the output of the first schmitt trigger to the input of the first and gate or the previously mentioned setup is correct and also if the signal going to the UCC is correct or not. I am attaching my scope shots for reference:
a)Green is Input to Schmitt trigger 1, Yellow is interrupter output

b)Green is OUTPUT of Schmitt trigger 1, Yellow is interrupter output

2) I have also scoped the output of the drivers and found that they work as they should. The only thing which worries me is that normally force the output of both the drivers to 0 , to stop the working of the coil when the interrupter is sending a logic zero ( oR off during that time). Here in my case i am getting both the chips outputting logic 1 which is fine because in the push pull it doesn't really matter whether both the chips output zero or one, only thing is that the should be same.
So do I need to rectify this or leave it as it is because what i think is outputting logic 1 continuously will stress up the UCC for no good reason. Also is it related t the previously mentioned problem of the interrupter logic and resonant frequency being fed in tot he schmitt trigger twice. ?? I am attaching the scope shots for reference.
a)Driver chips output

b)how the actual pulses look like

c)Yellow is output of inverting chip , green is interrupter signal.

d)zoomed in shot of the above mentioned.

Offline davekni

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #1 on: June 06, 2020, 07:32:49 PM »
The UCC chips will work correctly with high output levels for the off state.  They are not stressed in this condition.

The germanium diodes on the antenna input have some small leakage current.  If the two diodes are exactly matched, the voltage would be at 2.5Vdc.  The scope probe or meter used to measure this voltage will pull it down with 10meg (or whatever meter input impedance you have), to 1.1V in your case.  If your antenna signal is weak, probing this node might disrupt operation.
David Knierim

Offline prabhatkumar

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #2 on: June 07, 2020, 12:18:54 PM »
Thanks a lot davekni !! With your schematic now I am able to run the Tesla coil . Also you were very correct about the loading with oscillsocpe probe . I happened to observe this behavior and thought something was wrong. But now it seems to be good so far . I was thinking to power it with the mains now . But only problem is that I don't have access to a variac at this point and I have only 2 IRG4PF50WD igbt at this moment . Is this igbt suitable for this application ? Please let me know on this

Offline davekni

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #3 on: June 07, 2020, 07:39:07 PM »
For an SSTC at 240kHz, FETs would be appropriate for the half-bridge driving the primary coil, not IGBTs.  SSTC circuits are not zero-current switching.  Rather SSTC circuits switch at high primary current.  IGBT switching losses would be too high.  Also, IGBTs are designed for 15Vge.  This SSTCIII circuit provides 12V gate drive.  (I did swap IGBTs for FETs in one of my designs with 12V gate drive, but first checked my IGBT parts to see that they functioned well there.  It was a zero-current switching circuit, so didn't have switching loss issues.)

What half-bridge parts are you using now for low-voltage testing?  Are they IRFP460 as in Mads SSTCIII?

How is performance using your 60V 5A bench supply?  That's enough power for some reasonable sparks.

If you are already using IRG4PF50WD IGBTs, keep the enable pulse duty cycle low (short on times and long off times) and check IGBT case temperature.  Those particular parts look like they may work OK at 12Vge, although spec'ed for 15Vge as is normal for IGBTs.
David Knierim

Offline prabhatkumar

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #4 on: June 07, 2020, 09:55:23 PM »
Thanks for the quick reply !! For your igbt advice , I definitely understood what you are trying to say , so I rather stick with the FETs.
I am not using any common of the shelf like irfp460 and irp260.
I actually had a stock of around 6 pieces irfp260 from AliExpress and to be honest by looking at their casing only I could make out they were counterfeit. They didn't even have a genuine name stamped onto the plastic , just a dumb irfp260 written on with paint which you can easily scrub off.
So I had no choice but to use salvaged components as there is still lockdown in my place. I tested them the salvaged FETs with a component tester before and they were fine.
The FETs which I use are FQA38n30 . And they have a maximum voltage rating of 300v . But where I live (India ) , we have ac 230 v and after rectifying , the peaks could easily reach 330 v and above . So definitely I couldn't connect mains to it directly so I am limited to using a rather crude and dodgy setup which gives me around 130v DC.
 I use two 27 volt ( not identical so again a risk here ) transformer, and then connect them in series , and then connect it to a voltage doubler circuit . The voltge at the output when loaded with the coil is around 130v DC.
Another thing which is eating my head is that for now I was powering it with a single 27 transformer and voltage doubler . But the current draw seemed to be very low I guess , even after running for like 7-8 mins the FETs didn't even warm up . So I wonder if something is screwed up .
Please leave your suggestions on this 🙏😊.

Offline davekni

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #5 on: June 08, 2020, 01:51:18 AM »
In an ideal world, the only power dissipation is in sparks from the secondary top.  If sparks are short and weak, they aren't dissipating much power.  Of course, in this real world, there are other power losses, in FETs and winding resistance.  Sparks should still be dominant for power dissipation.

Presuming sparks from the top are minimal, low coupling from primary to secondary is my first guess.  Could also be too high a primary impedance (too high inductance for the frequency), causing primary current to be low.  One way to measure primary current is by voltage across C9 in the SSTCIII bridge schematic.  Knowing frequency and capacitance and voltage allows calculating current.  Double to get primary coil current, since half goes through C8 and half through C9.

Finally, if the half-bridge phase is too far off from secondary voltage phase, drive will be inefficient.  (Another way to say this, if phase is off, oscillation frequency will not be centered on the secondary resonant frequency, so secondary voltage will be low.)

A few pictures would be helpful, showing your primary and secondary, half-bridge wiring, and gate drive transformer.  If there is still too much parasitic wiring inductance, that could be causing the circuit to misbehave.

BTW, placing non-identical transformers in series is not a problem, as long as the load current isn't more than the rating of the transformer with the lower rating.  Of course, short-term higher current is usually fine for hobby use.  Paralleling non-identical transformers is more likely to cause issues, as their output voltages may not be identical.
David Knierim

Offline prabhatkumar

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Re: Gate voltage collapsing in KAIZER SSTC 3
« Reply #6 on: June 09, 2020, 08:46:02 AM »
First of all sorry for the delay. This is going to be a long post, so please bear with me. I will try to write attach wave forms wherever possible Now I would like to tell you few things about my setup. I have been using more or less very loose bird nest type wires. But today after your post I made many changes and then again recorded the current draw . But there were no difference. I made the wiring as short as I could . And because I am using a transformer and voltage doubler, I still have many wires running in the air , but that's the best I could do . The only thing which makes me worry is the waveform at the gates of the mosfet, it seems to collapse  a bit after reaching a certain value and then again starts to rise gain to reach the desired voltage. Now a few things which came to my mind on this issue. The first thing is that during the initial building of this coil, i faced big issues like blowing up UCC chips, which was later fixed by adding things like adding diodes at the outputs of the UCC to prevent latch up and adding a resistor in series to the GDT primary. Now i am not sure which of these changes fixed my problem. The addition of resistor in series of the GDT is not there in any schematic except for the One Tesla TS( the used a resistor in series with GDT of value 3.3 ohm and no resistor at the gate of the IGBT).

In my design i used a 3.9 ohm resistor which later even after reducing to 1 ohm didn't fix the voltage collapsing problem. And needless to say I even tried to go the One tesla approach, I removed to the resistor at the gates of the mosfet but still all i get is faster rise time but also there are some overshoots also but only till 14.4 volt, which I think shouldn't be a problem. Only thing which makes me worry is that even though int he short term operation is works fine but in the longer run there could be high frequency oscillation due to the missing resistor . please correct me here if I am wrong.

After removing the resistance on the gate of the mosfet.

Now the only suspect for the voltage collapse at the gates is the resistor in series to the GDT. What i think would be better is that yo remove the resistor in series to the GDT and instead place a resistor at the gates of the mosfet.
Also more Important thing is that due to this voltage collapse probably the sine current through the primary gets distorted, it occurs exactly during the duration of the voltage collapse. Is this a coincidence or really is it due to the voltage collapse problem.



Also could it be due to the crude current transformer setup( i use 1:100 CT ready made donut type terminated with a 47 ohm resistor). 
Another thing which is missing is the diode that speeds up the fall time , is the distorted sine wave due to it ?
Now I will attach pictures of my setup. In this you will notice that I have white colour power resistor (0.1 ohm) which I tried using as a shunt. But it didn't work out well. reason being I think is that I dont have a differential probe. So I do ch1-ch2 to get the voltage across the resistor. But that gives a bad noisy, blurry horrible to look at signal from which we cannot make out anything. Actually in place of the resistor, I had the current transformer whose picture which I have uploaded below.








Please let me know your views so that i can proceed with the solution.

Offline Mads Barnkob

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Re: Gate voltage collapsing in KAIZER SSTC 3
« Reply #7 on: June 09, 2020, 09:28:33 PM »
Now the only suspect for the voltage collapse at the gates is the resistor in series to the GDT. What i think would be better is that yo remove the resistor in series to the GDT and instead place a resistor at the gates of the mosfet.
Also more Important thing is that due to this voltage collapse probably the sine current through the primary gets distorted, it occurs exactly during the duration of the voltage collapse. Is this a coincidence or really is it due to the voltage collapse problem.

Please let me know your views so that i can proceed with the solution.

The collapse happens at the Miller plateau, here the gate drive needs to work extra hard to overcome the sudden rush of charge going into the junction. It seems your gate drive signal is too weak to overcome the Miller capacitance without dropping, but seen in the bigger picture, that is a very minimal drop over your 261ns rise.

Gate resistor value is about perfect when you have one little overshoot and no ringing, so do not change that, unless you change to a harder gate drive and might need to add more gate resistance to damp it.
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Offline davekni

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #8 on: June 10, 2020, 12:10:12 AM »
Much improved layout!  Especially good to see the two 1uF caps on VBus adjacent the half-bridge FETs.

Your gate drive waveforms look fine.  Mads explained the step well.  It is normal.

That current transformer may be good.  Most current transformers are for line-frequency use, but that one looks more like something from a switching power supply.  There is no way to know for sure without specifications or measuring it yourself.

Yes, differential measurements of small signals on top of a large common-mode signal is difficult.  To make the differential signal larger, I'd suggest measuring voltage drop across the primary coil series cap, the black cap at the back of your pictures.  (What value is that cap?)  That will give you the time-integral of current (current with 90 degree phase lag).  Knowing frequency and capacitance allows calculating the primary coil current.

Primary-to-secondary coupling factor looks very low for an SSTC.  I'd suggest spreading out the primary windings (space between each turn) and perhaps adding another turn or two.  Most SSTC designs I see here have the primary covering 20-50% of the height of the secondary.  Others here with more SSTC experience may have more precise suggestions.  Many have a piece of pipe or other insulating cylinder as a primary winding form to insulate it from the secondary, especially important at the upper end of the primary winding where secondary voltage is significant.  The primary winding form usually extends a bit above the top end of the primary to avoid arcs around the top of the form.
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Offline prabhatkumar

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #9 on: June 10, 2020, 05:09:29 AM »
Thanks for reply !! I still have a concern that why is the current getting distorted and not a proper sine wave. Is this a reason to worry because none of the builds I saw before have this distorted sine current . Also what could be the possible reasons for a weak gate drive signal ? In another topic by Max serienger , he also had this similar step well issue and to which later when he changed the china UCC chips to trusted UCC chips , the step well disappeard ( there could be other reasons for it too).
Also the current transformer is from an old big ups or some kind of power inverter , so I thought it would be appropriate for the job. There is no datasheet for this CT available.
And yes now I will also upgrade the primary to something beefy , and will also insulate the primary better .
The black primary blocking capacitor you talked about is a 4.7 uF mkp capacitor. Can you also tell me also how to measure current using that method in a little detail way
« Last Edit: June 10, 2020, 06:46:42 AM by prabhatkumar »

Offline davekni

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #10 on: June 10, 2020, 06:44:16 AM »
The gate drive waveform depends on where it is being scoped and where series resistors (and diodes if included) are connected.  If scoped on the drive side of any gate series resistors, then the step will not show up or be much smaller.

The distorted sine wave is a bit odd.  Part of it could be that the 1uF caps on the half-bridge are too low value to make VBus close to DC.  You could scope VBus at the half-bridge to see.  Another part may be the current transformer.  An old large UPC may have ran at 5-10kHz, so the CT may not be good at 200kHz.

It's also that few people measure SSTC primary current.  Most primary current plots here are for DRSSTCs.  I'd expect SSTC primary current to be closer to a triangle wave.  Perhaps your "distorted sine wave" is closer to a triangle wave modified by the two factors I mentioned above.  SSTC primaries are intended to not be resonant.  They will have a resonant frequency due to the coupling capacitor (4.7uF in your case), but that should be well below operational frequency.  So, if the caps are large compared to operating frequency, then the half-bridge is feeding a square wave into an inductor (primary coil).  Inductor current is the integral of voltage.  Integral of a square wave is a triangle wave.  Secondary resonance will change that shape some.  In your existing setup, coupling is low, so secondary current will have little effect on primary current.

For measuring current by voltage across the 4.7uF cap, it's the same as measuring voltage across the series resistor using two scope probes and subtracting the result.  The voltage across the cap will be larger, so easier to pick out from noise.
David Knierim

Offline prabhatkumar

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #11 on: June 10, 2020, 06:54:53 AM »

The distorted sine wave is a bit odd.  Part of it could be that the 1uF caps on the half-bridge are too low value to make VBus close to DC.  You could scope VBus at the half-bridge to see.  Another part may be the current transformer.  An old large UPC may have ran at 5-10kHz, so the CT may not be good at 200kHz.
Thanks again for the reply ! Please could you elaborate on what do you mean by " Vbus at the half bridge to see " and also "Vbus close to DC" . What is DC here ? And also about the low value of those 1uF caps , I have seen people use much lower values !
Also could you tell about the probing these points ?
And probing across the capacitor did not help , it was delivering horrible to look at signals

UPDATE: I am trying everything for the second time, the post did not allow me to edit the post and hence i ended up only posting the pictures of the progress I made.
So i went ahead and according to the suggestions i redesigned the primary and also made some tweaks. The spreading of the primary over the secondary made a great change and now I seem to pump significant currents.
New primary:

 After doing a few changes I checked the waveform at the output of the bridge and it gave me a horrible spiking square wave with spikes up to 165 volts even though my input voltage to the bridge was 140 V DC max.Waveform for the same:

So I tried doing some adjustments like moving the primary wire little bit here and there and also changed the resistor at the GDT input to 3.3 ohm ( I suppose, it will be explained later why supposed). Now it seems magic had happened the spikes were completely gone, i was getting max 3-4 volts spikes with the max and min going from 73 to -71 v).
waveforms :
Yellow us the output of the bridge.
. Yellow is gate Gate source voltage and green is the current through the primary measured by 1:100 CT terminated by a 47 ohm resistor.
I was pretty impressed by the performance and took a video recording of it( Cannot attach here since the size is big). The coil made pretty decent arcs for the voltage and it was horribly loud( so loud that my neighbors asked me what was i doing ( they did not complain , at least till now) ).
Sparks:
(Its a screenshot of the screen playing the video)

But now the sad story. After 2 hrs again, i started to experiment again and unfortunately i started getting spikes again, so i tried changing the GDT resistor value but now it seems again that were bad spikes of 118 volt. And i also forgot whether i had 3.3 ohm or 3.9 ohm resistor originally before i messed up. So I guess it was just sheer luck that I was getting no spikes. And also my self wound , not so great GDT started coming apart( the insulation and probably some of copper also broke , front the place i had put superglue on it to the GDT to add some stress relief).
But Now I think i will redesign this circuit with all the changes i made from the initial Kaizer sstc 3, on a piece of perfboard itself which will take good amount of time. I will also use tc4420 instead of the china UCCs( though tc4420 are also from china). I will have modify the logic circuit a bit since i will be using both thr drivers as tc4420 as I dont have the inverting tc4429. I also happen to few GDT from broken SMPS( 5 volt 20 amps). The GDT looks small , but I think it size is comparable to the p0584nl used in the one tesla and many other places. I also verified it with a function generator and fed it with a frequency of 240Khz which is close to the resonating frequency of my coil. I am attaching the picture of the gdt along with the waveform:
.
I also happened to find a GDT from another SMPS( 5v 40 A) which has a step up ratio of about 1.5-1.7. I think this would be nice for driving an IGBT.
 Please leave your suggestions on the new build I am planning with improvements also.
« Last Edit: June 10, 2020, 07:20:05 PM by prabhatkumar »

Offline ritaismyconscience

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #12 on: June 10, 2020, 11:07:34 PM »
That GDT doesn't seem to have insulation between the two wires, just lacquer. I've seen people make GDTs with magnet wire but I probably wouldn't risk the wires shorting and blowing up the IGBTs

Offline davekni

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #13 on: June 11, 2020, 05:49:58 AM »
Size of the capacitors at the half-bridge depend on how long wiring is from the electrolytic capacitors.  If it is all close with low-inductance connections (ideally copper planes), then small film caps work fine.  With spread-out wiring and its associated inductance, then the local film capacitors need to handle more of the current.

Scoping works fine as long as you are using a transformer for feeding VBus (the half-bridge power, from lower FET source to upper FET drain), then scoping is easy.  Ground the scope probe to the lower FET source.  Scope the upper FET drain, and then scope the junction between the two 1uF caps.  If powered directly from line voltage, then don't ground a scope probe to any of the half-bridge circuitry!  Ideally the voltage measured at the upper FET drain (voltage across both 1uF caps), and the voltage to the center point between 1uF caps, show mostly a DC waveform, with ripple say 20% or less of the DC value.

For DRSSTCs, the difference between clean and ringing H-Bridge output waveforms is usually proper phase lead.  If the H-Bridge switches just before current zero-crossing, the switching is smooth.  If after current zero-crossing, there's much more ringing.  SSTC designs generally switch well after current zero-crossing, so I suspect ringing is common.  Low inductance between the FETs and 1uF caps will help that ringing.  Higher gate drive resistance also helps by slowing down switching, but at the expense of lower efficiency (more FET power dissipation).

Hard to tell from the picture, but yes, if your new GDT is just enamel insulation, use it only at low voltage.
David Knierim

Offline prabhatkumar

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #14 on: June 11, 2020, 08:56:10 PM »
First of all thank you everyone for the reply !! Yes the GDT in the picture is just enamalled copper wire. I understand the risks of the secondary being at the mains potential. But what I think is that they should work just fine, because they were being used for the same application before. Just for clarity I will attach another closeup picture of GDT:

I also have another GDT which I guess would be safer since it does have some real insulation and not just laqer insulation. I am its picture also here. The only thing is that it has a step up ratio, which is definitely required for the IGBTs but not by most of the FETs which have typical 20v G-S breakdown voltage. But I needn't worry since the FETs i use currently( FQA38n30) has a G-S breakdown voltage of 30V. Second GDT:


Anyways, I again did some wiring change slightly and got decent waveforms. I removed the resistor in series to GDT, and added a 7.5 ohm resistance to the Mosfet gate. Now the horrible ringing is gone. I guess this ringing etc has also to do with oscilloscope probes, they do tend to pickup noise but maybe in certain lucky positions they dont. I also twisted the primary wires and that helped a lot. Now my output of the bridge doesn't have a lot of spiking, but something is again worrying me. I also had to reduce the area which the orimry covered ( basically more coupling) otherwise I was drawing huge peak currents in each cycle( 38-39) A even though my mosfet has a maximum rating of 38.4 A. Now my peaks are less than 25 A. Also, in one direction of the half bridge , something seems bit odd. I tend to have more spiking in that one direction and also the current waveform start looking odd, again unsymmetrical behavior. I believe this has to do with the fact that I did not add the reverse resistor bypassing diodes for faster turn of the FETs.
waveforms:

Yellow is gate source waveform of the lower side FET, Green is the current through the primary.

 Yellow is out put of the bridge, green is current through the primary.

Zoomed in version of the above.

When the oscillation just starts ( Interrupter on), the spikes are much higher. I wanted to know if putting a load resistor on the output of the GDT would help suppress this to some extent.
Also another thing which I curious about is why isn't there any gate to source pull down resistor like 10k in most of the normal mosfet applications. I did happen to spot that gate to source pull down resistor in the SMPS is salvaged the GDT from.

Now please advise me on the ringing more in one direction part and also unsymmetrical current( I somehow feel they are interrelated , maybe that resistor bypass diode but i am not sure about it ). I am also thinking to add a just a load resistor on the output of the bridge as i did see them in some designs. Maybe that will reduce the spiking to some extent. I also want to a snubber capacitor to the bridge. Where do I need to put the snubbing cap. I dont have a proper snubbing cap :( though. I have the same 4.7uF dc blocking cap which is in series to the primary. I think I will parallel two of them to get some work done. I am attaching the picture of the 4.7uF cap:


Thanks everyone in advance. Without the help of you people I could not have ever imagined to build my first SSTC and reach this stage.

Offline davekni

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #15 on: June 12, 2020, 04:36:11 AM »
The enamel-insulated GDT was likely for a low-voltage application such as synchronous rectification on the secondary side of the supply.

Two concerns with using the non-1:1 GDT:  One, the leakage inductance is almost certainly higher since the windings can't be paired as well.  That will add more ring to your gate waveforms.  Second, and likely more important, is the added load on your gate drive ICs.  The load they see goes as the square of the turns ratio.  So a 1.5:1 ratio will more than double load on your driver chips.  Check temperature carefully if going that route.

Your two gray 1uF caps are your snubbers.  Larger caps will help as long as wiring is short, especially with your long wires to the electrolytic bulk caps.  It can also help to have a cap across all of VBus (across the pair of 1uF caps), from bottom source to upper drain.  You can cut inductance in half by adding new snubber caps on the other side of the FETs, so they have separate short wires.  Larger snubber caps may make your current waveform closer to the expected triangle wave, as both VBus and the center-tap will be closer to DC (less ripple voltage).

Reducing primary area is decreasing coupling, but increasing primary inductance.  You'll likely get better performance by keeping the primary spread out, and adding a turn or two to get higher inductance.  It's the higher inductance that is reducing your primary current.

When using gate resistors on the secondary of the GDT, parallel diodes are recommended.  It will make gate-drive undershoot higher, but be more certain to avoid shoot-through (simultaneous conduction of both FETs).  Since your FETs have higher max Vgs, the undershoot shouldn't be an issue.  If undershoot is too much, either add a bit of series resistance to the GDT primary or a bit in series with each diode.

There's some interesting ~20kHz ripple on your half-bridge output.  Where is the scope probe grounded for that measurement?
David Knierim

Offline prabhatkumar

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #16 on: June 12, 2020, 05:20:35 AM »
First off thanks for the reply!!
The first GDT was being used in the primary side of the power supply to drive the two FETs which in turn drove the transformer. I could see the traces from the controller ic along with some complementary components as well as a push-pull converter either transistors. So I I am very sure they were being used for the gate driving of the FETs on the primary side only.
Thanks for the advice on the second GDT, it was definitely important because now I will know what might have gone wrong if my ICs ever blew up again :)
I will be using those two big gray Caps and see how they affect the performance.
I have deliberetely increased the primary inductnace so that less current flows through the primary , otherwise very high peak currents were flowing which were either too close the max ratings or even exceeded it.
I will also try with the diodes. But I have not understood what Is undershoot. Can you please explain me ?
Never noticed that 20khz ripple. I will do some measurements again and then zoom in send the waveforms here .

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #17 on: June 12, 2020, 05:46:11 AM »
Yes, I understand that you increased primary inductance.  I was just suggesting to do that with additional turns rather than closer spacing.

Undershoot on the gate waveform is the peak negative spike immediately after each falling edge.  The diode bypasses the resistor for falling edges only, reducing the damping.  GDT leakage inductance and gate capacitance will combine to make the resonant undershoot spike without the series resistor damping.

Perhaps, if the primary control logic is tied to primary voltage (so no regulatory safety requirements) and the primary voltage isn't too high, they got away with enamel insulation.  There are different grades of enamel, including multi-layer coatings.

One more thought on the half-bridge output ringing in some of your previous waveforms:  Perhaps that was caused by brief cross-conduction, where one FET turned on slightly before the other turned off.  Diodes across the gate series resistors are to insure no cross-conduction (no shoot-through).  Or, the version with a series resistor on the GDT primary and none at the gates works well as long as the GDT leakage inductance (and wiring inductance from GDT to gates) is low enough.  Then no diodes are needed.  That's the version I use more often for FET H-Bridges and half-bridges.  (IGBTs need a bit more delay to prevent cross-conduction, so the gate resistor and parallel diode option is better for driving IGBTs.)
« Last Edit: June 12, 2020, 06:32:02 AM by davekni »
David Knierim

Offline prabhatkumar

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Looking for SSTC DRIVER BOARD
« Reply #18 on: June 14, 2020, 07:21:50 PM »
Sorry for the long delay. I had working on another project meticulously for quite some time( Trying to build a fullbridge out of ir2110).
I had tested the system with snubber capacitor in place( I could install only one 4.7 uF capacitor because there was not even a tiny bit of space left for anything else on the board). Now the spikes decreased even further.
So I am kind of satisfied with the build, only thing is that now i want to make this better. The first thing is that my gate drive system is weak as discussed in the proevious posts. I had also tried to use the other GDTs but with no luck, the step well was still quite visible. This step well might cause big issues when running on higer voltages and when large currents flow. The current is still kind of broken like some of the previous posts and not triangular with a asymmetry quite visible.
So now I suspect that either the crappy Chinese UCC are to be the cause or probably something with the bad board design. Now I was going
through the options of making the gate drive stronger. I came across LONEOCEANS once again ( wonderful site full of great content):

Here P channel and N channel FETs are used to increase the current of the gate drive. Now I am always a fan of building a circuit on my own, but this time I had no option as due to lock down I cant go local electronics store to get the small items like resistors,capacitors etc.
So I want to order the LONE OCEANS board itself. Though he offers all the schematics, but he doesn't offer the Gerber files to order the boards from a site like JLCPCB or something else. I will order all the small parts like caps, resistors from mouser then.
If someone here happens to know where could I find a driver pcb for SSTC ( preferably LONE OCEANS, but other boards would also help).
Thanks in advance.

Offline davekni

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #19 on: June 14, 2020, 10:14:15 PM »
The added FET buffer stage is good for driving larger gate loads such as the IGBT bricks used in larger DRSSTCs.  Your gate-drive waveforms look fine.  The primary current waveform shape is likely due to the 1uF snubber capacitors and wiring inductance back to electrolytic bulk caps.  The primary current waveform isn't necessarily an issue.  It probably works fine as is.  Scoping the center-tap between the two 1uF caps and the half-bridge output would help explain the details.  But that doesn't mean anything needs to change.

If you want to work on improvements, I'd suggest making a crude ECB for half-bridge power interconnect.  This can be copper foil tape on either side of an insulating layer, or copper-clad board cut with a knife or moto-tool cutoff wheel.  Here's a crude image of one option:


One side, shown in yellow, could be half-bridge output on the right and the center-tap between the 1uF snubbers on the left.  The other side, shown in Red, could be VBus+ on top and VBus- on the bottom.  FETs could mount on the right, with appropriate source and drain leads bent up to solder on top of the board and the others out strait to solder to the bottom.  (FET packages parallel to the board.)  Snubber caps can solder to the left edge, or on top of the VBus side of the board with leads bent out for soldering.
David Knierim

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Re: SSTC DRIVER WITH NON FUNCTIONAL ENABLE PIN FOLLOWUP
« Reply #19 on: June 14, 2020, 10:14:15 PM »

 


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