Author Topic: My new half bridge SSTC design - with no GDT!  (Read 369 times)

Offline Irido

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My new half bridge SSTC design - with no GDT!
« on: May 08, 2020, 09:37:02 PM »
I just got done designing the PCB for my second ever Tesla coil! It uses a half bridge (duh) of IRFP260Ns with a maximum bus voltage of 170VDC (Nominal bus voltage is only 65VDC though). The MOSFETs are driven without a bulky gate drive transformer, by utilizing an IR2184 half bridge MOSFET driver IC. I think this may be the first half bridge Tesla coil using this IC, but that's not exactly a big achievement. It also has an optical receiver coupled to the shutdown pin of the IR2184, so it can be a musical Tesla coil, provided a MIDI interrupter is optically coupled to it.

The secondary coil is likely going to be about 1090 turns of 30 AWG wire on a ~90mm PVC pipe that's 305mm tall. It will have an extra 50mm of pipe on the bottom to fit into a 3D printed "socket". This socket will be on a 3D printed base plate that will be attached to the PCB with some M2.5mm male-female spacers. The secondary's resonant frequency will be roughly 417.3 kHz. The primary coil is going to be about 4 turns of 14 AWG wire. The socket will likely have little grooves for the primary coil to slide into to make it easier to wind. I should also mention that both coils are attached to the driver via screw terminals, so I can swap the coil between different drivers.

Here's the circuit schematic: https://imgur.com/a/qI3S42k

Here's the PCB: https://imgur.com/a/yL6CzOB
I designed the PCB to be 100mm x 100mm. It has 4 holes for M2.5 male-female spacers to go in so I can attach the coil mount to it.

As always, I would love to hear your constructive feedback on my SSTC design. Leave it in the replies please!
Anything can be a conductor if you pass enough voltage through it!

Offline Weston

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Re: My new half bridge SSTC design - with no GDT!
« Reply #1 on: May 09, 2020, 02:35:17 AM »
Nice to see you had the foresight to place mounting holes, I have forgot that on a number of my projects. Is M2.5 hardware common? I have always used M3.

Based on the gate charge of the IRFP260 you are going to need ~2W for gate drive, so if this is running in CW mode the gate driver IC or the gate resistors might get pretty hot. ~400KHz is a bit high for a SSTC and the gate drivers and FETs would run cooler with a lower secondary frequency.

If this is a half bridge, why are the connections for the two FETs broken out separately to the  terminal block? (looking at the data sheet for the gate driver it seems they show it connected this way, that diagram is not correct).

You want to have the source of the top FET connected to the drain of the bottom FET. This connection is part of the switching loop so you want it to be short as possible. One side of the primary should be connected to this switching node. The other side of the primary should connect to a DC blocking capacitor. People typically split the DC bus capacitor to two capacitors in series and connect to the midpoint of that. Here is one of Steve Ward's old schematics showing that: https://www.stevehv.4hv.org/SSTC1/FBSSTCsch3.gif

Speaking of the DC bus capacitor you possibly want a larger capacitor / an additional film capacitor which will have lower inductance. The capacitor forms part of the switching loop and extra inductance here will cause voltage spikes. The capacitor also sees a lot of ripple current in a half bridge. I don't think a small 220uF capacitor like that would be rated for the current.

Offline Irido

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Re: My new half bridge SSTC design - with no GDT!
« Reply #2 on: May 09, 2020, 09:47:37 PM »
M2.5 hardware isn't used a ton elsewhere, but it's pretty common in electronics.

As for the Fres, I'm probably going to add a topload to lower it, or at least a long breakout point.

Also, I doubt that Infineon is wrong about the half bridge drive. I've seen people use this IC configured like this in full bridge TCs, the only difference in my design is the omission of some flyback diodes on the bridge because they weren't necessary.

The capacitor is pretty beefy, it's rated for more than triple the voltage I'll be running the TC at, so any voltage spiking shouldn't be an issue. (I plan on running the bridge at 67VDC from a voltage doubled 24VAC source.) Also, the 67V power supply has a film capacitor and a large 3300uf capacitor in parallel with the output to filter it, so I didn't put them in the schematic. The 220uf capacitor is there just for additional filtering if I want to run the TC from a less smooth power source.
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Offline Weston

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Re: My new half bridge SSTC design - with no GDT!
« Reply #3 on: May 10, 2020, 08:12:03 AM »

Also, I doubt that Infineon is wrong about the half bridge drive. I've seen people use this IC configured like this in full bridge TCs, the only difference in my design is the omission of some flyback diodes on the bridge because they weren't necessary.


Perhaps there is some misunderstanding here. Are you connecting the primary across the header labeled U2 / DB125 or is there some other connection not shown on the schematic? If you expect it to work with the primary connected that way you really should try to draw out the expected switching waveforms / simulate it.

Even if bootstrap power would work in that configuration, with Q1 and Q2 driven out of phase you would never have a current path through the primary.

A half bridge would have the source of Q2 connected to the drain of Q1, and the load connected between that and something at VCC/2 (for AC a capacitive voltage divider works fine). Steve Wards half bridge SSTC design I linked as an example shows this configuration.

If you don't want to take my word for it, you can look it up online, or look at previous half bridge tesla coils. Here are some examples:

https://www.infineon.com/export/sites/default/_images/product/power/GateDriver/circuit_diagram/Half-Bridge-Diagramm.jpg_386882510.jpg from https://www.infineon.com/cms/en/product/power/gate-driver-ics/half-bridge-drivers/

http://www.irf.com/electronics/topology-fundamentals

/>



Offline Irido

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Re: My new half bridge SSTC design - with no GDT!
« Reply #4 on: May 10, 2020, 08:43:08 PM »

Perhaps there is some misunderstanding here. Are you connecting the primary across the header labeled U2 / DB125 or is there some other connection not shown on the schematic? If you expect it to work with the primary connected that way you really should try to draw out the expected switching waveforms / simulate it.


Edit: Am idiot, forgot that the transistors need to be connected together with the load attached to them and the ground. Other than that though, should my circuit work? I also added a 470nf film cap and another 220uf cap.
« Last Edit: May 10, 2020, 09:18:24 PM by Irido »
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Offline Weston

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Re: My new half bridge SSTC design - with no GDT!
« Reply #5 on: May 12, 2020, 08:24:49 AM »
Are you connecting the primary return to the midpoint of two capacitors? You should have two film capacitors connected in series, one connected to V-, one connected to V-, with the ground between them.

As for the routing of the power electronics, you should consider increasing the spacing between your high voltage traces and the ground pour. You should also try to minimize the length of the traces connecting the FETs and the decoupling capacitor to minimize inductance, which can cause voltage spikes that damage your FETs. Draw a loop from the + of the film capacitor, to the drain of the top fet, from the source of the top fet to the drain of the bottom fet, and from the source of the bottom fet to the - of the other film capacitor, the area of that loop represents your stray inductance, you should try to minimize it. Consider putting the film capacitors behind the heatsinks, centered between the two FETs.

I am working on a forum post elaborating some of this, but to illustrate the impact, here is a simulation showing the FET voltage with a loop inductance equivalent to a loop with a area of a couple of square inches (~100nH) vs a very small and well routed loop (~20nh). As you can see, it makes a huge difference in the maximum voltage across each FET and can possibly make the difference between blowing up your FETs or not.





Offline Irido

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Re: My new half bridge SSTC design - with no GDT!
« Reply #6 on: May 14, 2020, 07:45:08 PM »
Are you connecting the primary return to the midpoint of two capacitors? You should have two film capacitors connected in series, one connected to V-, one connected to V-, with the ground between them.

None of the schematics I've seen have those two caps, they're arranged in parallel with the voltage supply and the primary is connected directly to ground. Also, I'm not concerned about voltage spikes, because they likely won't be higher voltage than the IRFP260Ns are rated for. Also, the loop is only like 20mm x 50mm, so I don't I'll have too much of a problem.
« Last Edit: May 14, 2020, 08:21:31 PM by Irido »
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Offline Weston

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Re: My new half bridge SSTC design - with no GDT!
« Reply #7 on: May 14, 2020, 08:20:30 PM »
Excess stray inductance also leads to higher interference emitted by the coil and higher switching loss. The example was just a typical case, it's possible to have worse voltage spikes depending on your bridge layout. At 65V your switches might not blow up, but at a higher supply voltage it may cause issues. It's pretty easy to optimize the routing of the power stage and it can only reduce the chances of blowing up your switches.

For a half bridge or a full bridge coil you need a DC blocking capacitor on the primary. In steady state the average voltage across an inductor (like the primary) is zero. For a half bridge the average voltage on the switching node is ~ the input voltage /2. For a full bridge slight variations in the timing between all the switches can lead to a net DC imbalance. Either way, this DC voltage  causes a net DC current to flow though the switches and primary, only limited by the DC resistance. This leads to excess loss and can cause your switches to blow up.

For a full bridge you will typically see the capacitor in series with the primary (even for a non DR SSTC) like shown here: https://www.stevehv.4hv.org/SSTC2/SSTC2-03.gif

For a half bridge you could put the capacitor in series with the primary and connect the primary to the + or - supply rail. However, in those cases the capacitor starts out at ~ 0 volts and is has to be charged to Vsupply/2 when the half bridge first turns on, leading to a large current spike when the coil first turns on. If you use two identical capacitors in series across the power rail the midpoint voltage starts out at Vsupply/2. Also, in this configuration they act as a decoupling capacitor across the half bridge.

I am not really sure what schematics you are looking at, but ~ all the schematics for half bridge tesla coils I can find online show these capacitors: https://www.google.com/search?q=half+bridge+solid+state+tesla+coil&source=lnms&tbm=isch

In particular, I would like to use Steve Wards coil as an example, his designs all serve as pretty good design references:

https://www.stevehv.4hv.org/SSTC1.htm
https://www.stevehv.4hv.org/SSTC1/FBSSTCsch3.gif

Offline Mads Barnkob

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Re: My new half bridge SSTC design - with no GDT!
« Reply #8 on: May 14, 2020, 09:37:27 PM »
In regard to the half-bridge topology: You can design a half-bridge without a center-tapped capacitive voltage divider and run your load between the two MOSFETs and ground. BUT! That will only give you a positive pulse on the output. The bottom MOSFET would be needed to discharge a capacitive load and if you want to drive an inductive load, anti-parallel diodes are needed.

So Weston is technically correct (the best kind of correct) that all solid state Tesla coils are using a capacitive voltage divider as you need both the positive and negative pulses. Some people think that the voltage divider is only there because Steve Ward used it as a voltage doubler in some of his circuits, it is however just a good use to extend an existing topology.

Here are some general SSTC design calculations, including how to calculate the correct DC blocking capacitor: http://kaizerpowerelectronics.dk/tesla-coils/sstc-design-guide/

http://www.kaizerpowerelectronics.dk - Tesla coils, high voltage, pulse power, audio and general electronics

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Re: My new half bridge SSTC design - with no GDT!
« Reply #8 on: May 14, 2020, 09:37:27 PM »

 


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