High Voltage Forum

Tesla coils => Dual Resonant Solid State Tesla coils => Topic started by: Netzpfuscher on December 28, 2017, 07:28:02 PM

Title: Next Gen DRSSTC
Post by: Netzpfuscher on December 28, 2017, 07:28:02 PM
I'm working on this coil for a while now. Now I reached a point where it's almost finished.
I used Steves UD3 driver with small modifications and made a huge code rewrite. The CPU of this driver is a Psoc5LP Cortex-M3 micro, which has a on board FPGA.
The software consists of a FreeRTOS operating system and a bunch of tasks which handles all the control functions. The interrupter is a piece of software inside the driver. I worked a lot to get the software as userfriendly as possible. The PC-Interface connects via USB to the PC and enumerates as USB-Midi and USB-Serial Port. You can connect to the serial port with a vt100 terminal and the driver offers you a CLI with autocomplete, history and help functions.



The driver can sweep through a given frequency range and plot the response of the primary and secondary for easy tuning.

Primary:

Secondary:


Interface:


The driver samples the maximum primary current an displays it in the status window (Youtube Video). It measures the Voltage on the bus and the current to the bus to calculate the rms current and the power.


The driver board:


The complete coil:


The inverter box:



To handle the peak powers I build a buck converter to reduce the 3 phase mains voltage (565V in Germany) to 400V which is the maximum voltage of the capacitors at the moment. The buck is calculated for 10kW continuous power and waits for a enclosure  ;D



At the moment I'm working on a new PCB which includes the secondary current circuit and a small fix at the USB-Port.


I would put the complete code and the PCB-Design files on GitHub if I get the permission from Steve (90% of the PCB, the Logic in the FPGA and a little bit of software which I haven't rewritten is his work)

Title: Re: Next Gen DRSSTC
Post by: futurist on December 29, 2017, 05:58:18 PM
Big thanks for sharing your results!

I've been playing with lower-tech UD+ for some time now and I use it on my DRSSTC. It's a really nice upgrade from UD2.7C I've been previously using, and Hydron did some tweaks to the VHDL code to make SIG and OCD LEDs more visible. So far there isn't a single writeup of someone using the driver and/or potential problems they encountered, which I hope will change in the future.

Until now I didn't see any details about UD3, except spec sheet (https://docs.google.com/document/d/1Bm-FXaXNVYp29zDJLbYlqE-bow6KqK9jpyYCS02qUsA/pub) written by Steve. I'd like to see it gets public like UD2 and UD+ and I'm looking forward to building one. Do you know what does Steve think about releasing UD3 to the public?
Title: CW coi
Post by: Hydron on December 30, 2017, 09:45:51 AM
Looks great now that it's nearly finished!

I assume you're using 1200V silicon, and that the 400V limit is because you're trying to maximise the energy storage of the electrolytics by running 3 in parallel rather than 2 in series? Or can the IGBTs not handle the 565V either?

I am very interested in using and adding to your work if it can be released. I am currently building a phase-shift modulation QCW coil, and while the hardware design is well advanced, I am inexperienced in coding and VHDL, so that is going very slow (I currently just have a simple driver running on a FPGA dev board, and have not added a MCU yet). Anything with the sort of functionality that you've managed to implement would be a huge help (especially if the RTOS makes it easy to add tasks, e.g. for controlling a PFC boost stage), though I'd be doing my own PCB design.
Title: Re: Next Gen DRSSTC
Post by: Mads Barnkob on December 30, 2017, 10:02:57 AM
Welcome to HVF Netzpfuscher :)

I really like the idea of a terminal/cli controlled coil, OS independent.

Built in tuning functions, surveillance sensors and MIDI, what is not to like. I was wondering if your interface/driver can be networked/cascaded for multiply coils running on each their midi channel?

Great work so far and I hope you find a solution with Steve, he has a good record for publishing his stuff and only stopped because he spend too much time supporting others building from his plans.
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on December 30, 2017, 12:13:38 PM
@Hydron
Yes I'm using SKM200GB124D IGBTs. The inverter was intended for developing the firmware, not for maximum streamer length. Therefore for the ease of building the bridge I only used one cap. I ordered a box of 40µF 1100V DC-Bus film capacitors with a rms current rating of 21A each. If I have time I build a MMC for the DC-Bus with around 500µF.
With RTOS it is very easy to add other functions, there are a lot of CPU cycles free.

@Mads Barnkob
The cascading feature is on the way ^^ the hardware is there. I used little daughter boards for the fiber conversion. On the connector are two UARTs so it is only a software thing to add this feature. Then the master coil filters on the MIDI-Channel and relays the messages to the other coils.
The CLI is a little bit trickier. I think I use a command for switching between the coils like "switch coil2".

 [ Invalid Attachment ]

The other way is to use WIFI daughter boards. I have a working prototype with a ESP8266 which acts as a MIDI-RTP (Apple MIDI) and Telnet Server. But the timing over WIFI is not very accurate.


Title: Re: Next Gen DRSSTC
Post by: Steve Ward on February 18, 2018, 07:00:45 PM
Just wanted to say how great it is to see Jens expand upon the UD3!  I'm at a point where im sure im not gonna pursue any for-profit business with my work with Tesla coils, so I'm totally fine with releasing design/code, so long as my name gets in there still :-).  The main reason UD3 isn't out there, easy to find and download files, is that it's quite an undertaking to build one and make it work and supporting others in that effort is quite time consuming, so i've been limiting its release to a few people that have contacted me.  Jens seems to be quite at home with embedded programming, so I hardly had to do more than send some files over and he took it from there.  I've had quite a time supporting other guys who were totally new to coding, but eventually everything worked out.

Wanted to mention that UD3, with its extra HVDC sensing inputs, DC current sensor input and the few unassigned digital outputs, is capable of controlling a PFC or buck stage in addition to its usual TC duties (and it can also do phase-shift bridge control).  I have code for both of these instances (the buck driver code is really hacky... but it works) so if someone is really wanting to take this on, i can send code.  Of course, it's not at all compatible with what Jens has done here!

The tuning plots are really slick... did you add an extra CT input to get the secondary response?  Im sorta confused about what the difference is between those 2 plots you show... since the Fres dropped and another peak showed up, my guess was that the first plot was primary only (secondary physically removed) and then second plot had the secondary in place, but it says 0.3A which to me means you have a CT on the secondary ground lead.


Title: Re: Next Gen DRSSTC
Post by: Hydron on February 18, 2018, 11:59:59 PM
Steve - thanks for releasing this out there (and for all the previous UD drivers - most of us got our coils going with one of them!). If I can help with documenting how to use the UD3 without hand-holding I will (though it'll be a while before I understand most of the code myself - hardware is more my thing!).

As for the response plots - there is indeed an extra CT input, using the same circuit as the CTout net but with a 5R burden resistor. Once I get something up and running myself I'll be comparing the plots to what I get out of a FRA instrument (which also gives the primary, secondary and split-poles).

I'm personally also interested in the PFC possibilities/code, though I have a lot of work to do on my coil before I get to that part (and would also need to understand FreeRTOS more before I start adding tasks/code to Netzpfuscher's work). Will PM with my email address.
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on February 19, 2018, 09:20:44 AM
Yes I added a extra CT.

Steve you are right, the first plot is without secondary and the second plot is with the secondary in place. The primary capacitor needs to be bridged while plotting the secondary.
I think we should add a autotune lockout if the bus voltage is higher than xx Volts. The peak detection is done in analog hardware, so the ADC has plenty of time to digitize the peak current. The peak detector consists of a sample and hold and a comperator. If the interrupter signal gets high the sample and hold is enabled and tracks the maximum peak. If the interrupter gets low the ADC kicks in and digitizes the voltage from the sample and hold. If the ADC conversion complete signal goes high the sample and hold gets zeroed. I think I post a picture later.
I think we can use this circuit to tune the "max_current" parameter, we can add a factor which is controlled by the peak detector. If you dial in 400A max_current trip point and during run the current goes higher, the factor is set to for example 0,8. Then at the next cycle the overcurrent trips at 320A.

The analog processing in my code is done asynchronous. The ADC fills a buffer and at a certain level the analog task gets a semaphore. The complete buffer gets processed and the task goes back to sleep. This is a problem to implement a buck or a pfc. There is work to be done. I removed nearly all of the float calculations and the square root, because this is very expensive on a cortex-m3. The calculations are done with integer arithmetic and the sqrt is a approximation.
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on February 20, 2018, 07:43:59 AM
The git is online. For now only the firmware. The PCB files follow.

https://github.com/Netzpfuscher/UD3_PSOC

This is the last working version. I'm working to update to FreeRTOS 10 which isn't running yet, I get a out of heap error :(. If it is running I will add a development branch.
Title: Re: Next Gen DRSSTC
Post by: malte0811 on February 20, 2018, 09:03:19 AM
Thanks for uploading it! I had a look at some of the files, the copyright header doesn't look like this is supposed to be on GitHub/public ("CONFIDENTIAL AND PROPRIETARY INFORMATION", and it looks like you forgot to fill in the owner's name)? Is that intended or did you forget to change it?
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on February 20, 2018, 09:16:40 AM
I forget to change it. This is the standard header from Psoc-Creator. I think I clean it up with the next commit.
Title: Re: Next Gen DRSSTC
Post by: Hydron on March 04, 2018, 10:34:17 PM
I've managed to get the UD3 code up and running on a CY8CKIT-059 PSoC dev board (see http://www.cypress.com/documentation/development-kitsboards/cy8ckit-059-psoc-5lp-prototyping-kit-onboard-programmer-and), and it's happily running my hacked-up QCW coil using both the serial/USB CLI interface and USB midi input.

See the attached pic of the rats nest of cables I was using to run it - breadboard with PSoC PCB is above the mousepad (bench PSU power has now been replaced by a variac+isolation transformer and things have been tidied a little!). I also took a quick video of it running at 130V on the bus (obviously more space will be needed to put real power through the coil!):
/>


I have run it up to ~170V on the bus, though I am running into issues much above 130-150V with interference occasionally causing the controller to lose ZCS sync - probably not a surprise given how messy it is. The spikes on the hard switched transitions (in QCW phase shift modulation mode) are also quite large and a little worrying - I will need to look carefully at the PCB layout of the bridge and the gate drive resistors etc to see if I can tidy it up a bit.

To get it running on the dev board + breadboard setup I had to do a bit of work changing it to compile on the (slightly) different PSoC part, and have a few goes with pin selection to get the analogue routing to complete. I haven't had time to look at much of the code other than this stuff, though I do intend to get in and add/change things, and to have a go at getting an interface other than a serial console working.

Thanks to Netzpfusher and Steve for their work - has been fun getting it making sparks, and has helped hugely with testing things before I do any more PCB/software design for my coil.
Title: Re: Next Gen DRSSTC
Post by: profdc9 on March 05, 2018, 01:30:23 AM
It would be nice to have a version of UD 3 that uses the CYC8KIT-059 PSoC dev board for the PSoc 5 chip.  I have a couple of these dev boards, and they are very cheap, around $10, and very easy to use.  Perhaps a UD board could be made that is simple to assemble without exotic soldering techniques, and then has a pin header over which the  CYC8KIT-059 is plugged in to.  Is there a schematic for the UD3 showing how the chip is used, because as long as none of the committed pins for the dev board are used in the UD3 design, I think this should be possible.
Title: Re: Next Gen DRSSTC
Post by: Hydron on March 05, 2018, 09:43:43 AM
This is exactly what I discussed with Mads on IRC - it's definitely possible to lay out a board using a PSoC dev board + headers as a "through hole" part, and the dev board is _cheaper_ than the chip by itself. I'm probably not going to do such a layout myself (gonna stick to SMD), but am happy to help someone who is. BTW I disagree that soldering a QFP counts as "exotic", but the cheaper argument remains, and the dev board also comes with a USB connector inbuilt and even a whole extra PSoC chip (the programmer chip could be re-used as another mini dev board if you don't need many pins!)

The only reason I haven't posted more detail is because my setup is such a hack, and while all pins are routed on the PSoC, many are un-used. I just have the gate drive pins (going to another PCB with the actual drive circuitry on it - the green board in the top of the attached pic), UVLO shorted to +5V, CT current-sense and ZCS pins used. I've attached a close-up of the breadboard setup (note that while there is a crystal on there I couldn't find the right load capacitors in my parts box so I'm using the internal oscillator, which is really good enough anyway).

The biggest thing to watch for is to make sure that all pins can be internally routed to the required places on the PSoC chip - there are some restrictions as to what pins can go where on the chip, and limited routing resources (especially for analogue), so I had to shuffle some pins around the chip until the PSoC creator software could find a way to route everything. The other thing that should be done (but doesn't have to) is to adjust the speed that the PLL is running at - the PSoC dev board has a faster version of the chip than the UD3 design, and can run up to 80MHz rather than 67MHz (actually set to 64).
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on March 05, 2018, 10:48:54 AM
TQFP is easy to solder with a normal soldering iron.
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The price is definitively lower with the dev-board. But there are some points to save money on the board, I used gatedrivers from Micrel which are a lot cheaper than TI. For the GDT-output stage there are cheaper mosfets from Diodes (DMC3021LK4-13). The DCDC Converter is a 7805 compatible device, which can be sourced from china. Perhaps we can change the board and add the DCDC from the UD+.

You must be careful if you run the chip at 80Mhz. Some of the logic uses the 64Mhz PLL as Clock, I'm not sure if all of the timing calculations works correctly. Thats a thing to check before cranking up the speed.
Title: Re: Next Gen DRSSTC
Post by: Hydron on March 05, 2018, 11:06:11 AM
Yes, that's why I haven't changed the clock speed yet - I saw some stuff in the code that would need to be changed before the PLL frequency can be set to 80MHz.
Title: Re: Next Gen DRSSTC
Post by: Mads Barnkob on March 07, 2018, 06:45:14 AM
Great progress Hydron, the complexity of your rats nest has also grown over time, it used to be two probes and a single board :)

Could some of your switching spikes be due to low voltage DC bus and the output capacitance is playing you a trick? About the interference, I would get things boxed up and shielded before looking more into that.

I would still prefer a through hole driver board with a pin header for the dev. board, the only downside to this would be when the dev. board is discontinued from the manufacturer and suddenly it would be a bigger job making that yourself than soldering in the actually chip on a UD.

Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on March 07, 2018, 01:51:24 PM
To the interface. I think we should go with a industrial standard protocol for the standalone interface. Something like Modbus RTU, DMX or CAN. The Hardware has enough resources left for a second UART transceiver. The protocols can be implemented in tasks, it should be no problem to implement more than one protocol and execute the task according the config in eeprom. Yesterday I got FreeRTOS 10 up and running. I haven't tested everything, but I think in the next days it all works fine. The main feature why I upgraded the RTOS is the new streambuffer in FreeRTOS 10 this should improve the performance of the UART.

It is also possible to add WiFi or Ethernet to the UD3 with a ESP32 or ESP8266, I have a proof of concept on my hard drive.
Title: Re: Next Gen DRSSTC
Post by: Hydron on March 07, 2018, 04:05:47 PM
Anything that works over a <5MBps fibre link should be fine. Not sure how you'd do CAN, but the RS485/RS232 based protocols will work fine with fibre as the physical layer rather than differential twised pair copper, as they're basically asynchronous serial at heart.
Absent something more standardised I had actually thought of re-purposing a RS485 protocol we use for CCTV control at work (mainly because there's well-debugged code that I could re-use, though not release), but using something standard and open-source would be best.

I'm just putting together a Mouser order for UD3 parts, and the 80MHz speed grade part (CY8C5888AXI-LP096) is barely more than the 67MHz part, so I'll build a board up with one of those and have a go at increasing the clock frequency (work on the clock speed will likely be delayed by a long vacation though).

Lastly, I'll probably have a go at running my coil outside at full mains voltage in the next few days - will try and get video of the success/destruction.
Title: Re: Next Gen DRSSTC
Post by: Hydron on March 11, 2018, 11:17:45 PM
So I got the coil running outdoors, unfortunately with wind and in the middle of the day so no worthwhile video, but I have attached a pic of the setup taken from the "control room" (upstairs window where the variac, scope and PC were):
 [ Invalid Attachment ]

Control was via serial over the orange fibre optic lead, and I was able to look at bridge output current/voltage using a pearson CT and a couple of differential probes. The heater that can be seen is acting as ballast for my poor 2A Variac so it won't blow it's brushes to bits trying to charge the caps after each burst :P

The test was a success in that nothing went pop at 360VDC on the bus (variac cranked up to 11 on 240VAC supply), but the coil didn't behave that well otherwise. The spikes seen when hard switching were rather extreme, at up to ~750V (that may be a little high - I know that the probes used will ring themselves due to parasitics of the leads they use, but having checked with other standard 100x probes, I know the spikes are still there and large). This seems to cause the controller to lose ZCS synch, and causes waveforms like the following throughout most of the burst:
 [ Invalid Attachment ]

I'll be looking at the code to see if it can be made more resilient to noise, but to really fix things I think I'll need to get a revised version of the coil running with better layout etc (and higher current capability with 4x the number of IGBTS - was hitting my 225A limit a lot!). It has been really useful building up part of the bridge as a small scale prototype though - I've learnt a lot about what I should do for the final coil and will probably re-use some of the spare parts to make a smaller coil in the future.
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on March 12, 2018, 08:01:52 AM
I've tried to interpret your scope shot.



It looks like there is a overcurrent event and the driver goes to the freewheeling mode. But I don't know if it should do phaseshift during the ringdown. I haven't tested the QCW mode very much because I have a big low impedance coil. The big mess is under ~90A primary current, what CT ratio did you use?

The input comparator stage has a threshold which is defined in ZCDtoPWM.c:

   //set reference voltage for zero current detector comparators
   ZCDref_Data = 25;

If I find a little bit time, I can do measurements at my coil to see if there are problems with the logic.


Title: Re: Next Gen DRSSTC
Post by: Hydron on March 12, 2018, 08:23:55 AM
Yeah I was thinking about overcurrent, but didn't expect it to do phase shift during ringdown. The threshold is also set to 225A, rather than <150A where it seemed to trip earlier. Later on in the burst it does trip at the correct point, as seen below (QCW modulation finished by this point):
 [ Invalid Attachment ]

And another with odder behaviour (overall view, part of interest at division labelled 16.05ms):
 [ Invalid Attachment ]

Zoomed in:
 [ Invalid Attachment ]

I am still suspicious that there is some element of interference from the hard switching spikes happening here - behaviour seemed better when I'd reduced them by modifying the bridge. Unfortunately I don't think I'm going to have a chance to work on the coil again to test anything until about this time next month, however I will have a go with using the UD3 (and also taking some arc current measurements) on a larger DRSSTC if time permits.
Title: Re: Next Gen DRSSTC
Post by: Steve Ward on March 26, 2018, 03:54:22 AM
Phase shifting will remain in effect during current limiting, which does tend to make for unusual-looking waveforms as the phase shifted gate signals are still applied alternately between the 2 outputs.  It does appear that there's some phase error in your switching, still, which is a typical side effect of the the current limit function combined with the phase-shift control. The phase-shift bridge switching scheme gives a rise in operating frequency because the driving voltage pulses are leading by a significant phase compared to the primary current.  When it switches to freewheeling/current limit mode, the applied voltage is basically zero, so the phase lead of the driving voltage no longer comes into play, and so the frequency of oscillation will drop.  Toggling quickly between these modes is tricky for the phase predictor thingy and so it misses ZCS by a decent amount under some conditions.  Ideally, your QCW coil is designed so that it does NOT current limit while phase shift modulation is applied.  A few hard switchings should not be a significant problem for a properly designed bridge.

All that being said, did you follow the same schematic as the UD3 for the CT input?  Those filter caps are pretty essential i think... routing long wires to the dev board might be iffy around tesla coils :P.

I used 15 ohm turn on gate resistance with the FGH60N60 IGBTs and i use 2:1 GDT ratio to step the 24V drive to 12V as we are not abusing the peak current rating of the IGBTs in QCW coils.  Be sure you have sufficient dead time in your gate drive to avoid hard commutation of the output voltage.  What i mean is, the IGBT should always switch off early enough so that the primary current causes voltage commutation at the half-bridge output and the IGBT turn on is at zero voltage (ZVS).  If there is not enough deadtime, you will switch the IGBT on before the voltage at the output has changed, and this rapid charging of the other IGBTs junction capacitance can ring at very high frequencies with the stray inductance of your bridge.  Also, if the IGBTs are switching late, and the IGBT turning on must force the opposite diode to recover, this will lead to large spikes as the diode recovery is a high di/dt across the stray inductance.  I observe very nice switching waveforms on the 60n60s even when hard switching in phase shift mode.  Perhaps 50V maximum overshoot with 400V bus and 60A peak current per device.  Going easy on the turn-on seems like a good, simple choice to combat all the downsides of insufficient deadtime or too-hard-reverse-recovery of the co pack diodes giving big voltage spikes.
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on May 09, 2018, 12:41:22 PM
I've made big progress on the UD3 software. The command line now supports more datatypes:

-uint8 / uint16 / uint32
-int8 / int16 / int32
-float
-char
-string

The EEPROM-Dataset is revision save. With the new function it is possible to change the parameterlist and still read the EEPROM to the new parameterlist. The EEPROM function gives a warning if it can't find values in the EEPROM for a new parameter and it warns if there is a value in the EEPROM but not in the firmware.

The next thing I'm working on is a terminal for the UD3. It's based on Chrome App (Javascript) and should run fine on Windows/Linux/Mac. It includes a simple MIDI player which sends the MIDI messages over UART to the UD3 so you don't need a special Interface, a normal USB-UART is fine.

Title: Re: Next Gen DRSSTC
Post by: profdc9 on May 09, 2018, 05:44:23 PM
Do you have an example of the interface circuit between the microcontroller UART connection and the MIDI interface? 

Also, I was wondering if it would be possible to connect one of the ESP8266 wireless modules to it and use that for a serial port.  There's a serial to wifi interface here

https://github.com/jeelabs/esp-link

so it would be possible to use Wifi to talk to the terminal rather than USB.  The serial port is totally transparent and as long as there is TTL serial on the microcontroller side you don't need to do anything.  You just have to flash the ESP8266 with this firmware and it becomes a serial to wifi interface with a serial port.  You can get a ESP8266 module on ebay for like $2, and a CH340 to ESP8266 interface for about $1.50.

Thanks,

Dan
Title: Re: Next Gen DRSSTC
Post by: Hydron on May 09, 2018, 06:36:53 PM
I look forward to playing with the new code! I have been busy/away so haven't had much time to play with the existing stuff other than some more bench tests with my CY8CKIT-059 based QCW prototype (focusing on the power side of stuff rather than software).

profdc9:
As for serial, the command-line interface also comes up on the TTL TX/RX port in exactly the same way as the USB-UART interface, so it would be easy to talk to the ESP8266. The only thing you might need to check is what the UART speed is set to in the cypress design files. I have used this feature to connect via a fibre-optic serial link (see orange wire in post here: https://highvoltageforum.net/index.php?topic=188.msg1778#msg1778 )
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on May 09, 2018, 10:28:13 PM
It should be no problem if you use a transparent WIFI-Bridge. You can send terminal commands and MIDI commands to the TTL-UART on the UD3. The UD3 separates these and route the messages to the MIDI-Interrupter task or to the command line task.

With the new terminal there can be a second option. It is possible to implement a TCP or UDP connection to the ESP8266 over socket. This eliminates the need of a virtual com port driver on the computer side. But the WIFI-Link adds a few ms jitter to the data (MIDI), if the WIFI-Link is weak or there is a lot traffic it sounds a little bit wrong.
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on June 17, 2018, 08:35:38 PM
The first test of teslaterm was a success  :D There is still a lot of work to do and improvements to make, but it's running.

UD3-Firmware with teslaterm support:
https://github.com/Netzpfuscher/UD3_PSOC/tree/new_CLI

Teslaterm:
https://github.com/Netzpfuscher/Teslaterm

For running Teslaterm (drop the folder on the nw.js executable or make a link like this: "C:\nwjs-sdk\nw.exe c:\git\teslaterm"):
https://nwjs.io/


And the demo:
Title: Re: Next Gen DRSSTC
Post by: Hydron on June 18, 2018, 11:46:44 AM
Ooh, looks very interesting - thanks for the update. I'll let you know when I've had a chance to test it myself.
Title: Re: Next Gen DRSSTC
Post by: Mads Barnkob on June 18, 2018, 01:48:11 PM
That is a super cool interface and the trend feature is something that can make me order a devkit at once to try this out myself :)

I do however not feel like I have a complete overview of what parts and bits are needed as you all seem to run this on different hardware :o
Title: Re: Next Gen DRSSTC
Post by: Hydron on June 18, 2018, 04:27:14 PM
I'm not so up to speed on the code for the "interface" PCB (seen in first post with LCD), but the UD3 code will run on either of two boards:

1) the UD3 design based on Steve Ward's work and updated by Netzpfuscher (not sure if he's released the files for this publicly). This board comes with primary and secondary CT inputs, USB, UART header, relay/fan control, bus voltage/current monitoring, and GDT driver. No changes necessary to compile/run

2) A PSoC5 dev board, connected to (at a minimum) a CT and external GDT driver. This needs the pinout and device selection of the PSoC project to be changed before compilation, and some support circuitry either on a breadboard (as I did, see pics) or on a support PCB like what profdc9 designed. Ironically the dev board is cheaper than a single PSoC part despite having TWO devices on it (one for the programmer/debugger, which you'll need anyway for bringing up a UD3 PCB).

Both of these boards let you connect via USB (it enumerates as a virtual serial port + USB MIDI controller) or a straight TTL UART connection to the appropriate pins. I believe it falls back to UART if USB is not present, but not 100% sure.
When I used it the PC got very unhappy with EMI when using the chipset-native USB2 controller, but was happy with the motherboard's non-native USB3 controller (operating in USB2 mode). Dunno why one was OK and not the other, but I do know that USB is pretty garbage from an EMC immunity point of view, so you'll probably want to hook up to the serial port via a fibre link for proper full-power testing.
The primary interface via serial port is a command-line (as seen in the video and screenshots); I have not investigated properly what other methods can be used for control as the CLI has worked so far for what I have been testing.
Title: Re: Next Gen DRSSTC
Post by: profdc9 on June 18, 2018, 09:07:28 PM
I built up my PsoC 3 board.  The only things missing are the precision resistors for the voltage bus sensing, and the bus Hall-effect current sensor.  I have tested the microcontroller and verified that it can drive the gates however.   I haven't put it in a coil yet though.  The board for this is in the DRSSTC PCB pack.  The one in there is slightly modified because I moved a few components around to make the USB connector easier to access.



I modified the project for the new pin assignments.  You can get the file in 7zip format below.  It doesn't have any of Netzpfuscher's Tesla term modifications yet though.  I also modified the serial port speed to be 38400 baud rather than 2 Mbaud, because I will probably be using this with either a ESP8266 (which I have used successfully) or with an optical transmitter and receiver.

https://drive.google.com/open?id=19qv76rRRxeaazcwBBeACj1WtnnMVr_3k

One note:  when putting the PSoc5 into the pin socket, you might need to bend the pin sockets in slightly because if they are bowing out, they will tend to push the PSoC5 out of the sockets causing loose connections.  I think this is because it is difficult to get the pin header socket to stand up perfectly straight when soldering it in so you have to tweak it.

I probably won't have time to try this, but I would like to, but I am having too much fun with the UD2.9 skip pulse to take the coil apart, but I will probably try this driver eventually.

Dan
Title: Re: Next Gen DRSSTC
Post by: Hydron on June 18, 2018, 11:18:56 PM
Hah, I was wondering why you were complaining about not having room to fit everything on the PCB, now I understand! (Has been a while since I've done anything with much through-hole stuff on it other than TO-247 half-bridges)

It will run just fine without the sensing stuff (see my minimal breadboard on the first page), just doesn't report anything.
Title: Re: Next Gen DRSSTC
Post by: profdc9 on June 19, 2018, 03:19:15 AM
Yup the PCB is packed.  There's stuff underneath the PSoc5 chip too (low profile resistors and diodes).  Almost every square millimeter is used!

Dan
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on June 19, 2018, 08:14:00 AM
The PCB files are on Github:
https://github.com/Netzpfuscher/UD3_PCB

This design is untested due to a lack of time ^^
I would be very happy if someone helps with the UD3, we need documentation (Git Wiki). A SMD version with Kicad would be a big thing, Altium is to expensive. If we go with the same processor like on the dev-kit (QFN), we only need to maintain one software. I haven't found a good solution in PSOC-Creator to handle more than one processor.

@profdc9
The esp supports way more than 38400 baud. Perhaps the serial bridge software can be modified? If you want to use teslaterm the datarate can be a little bit slow. It works but the terminal can be little bit slow. While a chart/gauge frame is transferred the output of the CLI is blocked, so there can be a delay up to 145ms (70 bytes).  I have a missing option in teslaterm, there is no baud-rate selector :o
Title: Re: Next Gen DRSSTC
Post by: Mads Barnkob on June 20, 2018, 11:26:14 AM
I would be very happy if someone helps with the UD3, we need documentation (Git Wiki).

I would like to help, but consider me as a completely blank and new guy on that job, I would need a fairly detailed work list :)
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on June 20, 2018, 02:26:29 PM
I added a little bit of documentation to the wiki.  8)

https://github.com/Netzpfuscher/UD3_PSOC/wiki
Title: Re: Next Gen DRSSTC
Post by: profdc9 on June 20, 2018, 03:15:09 PM
If it would help you get started with Kicad, I put together a quick SMT board.  However, I used the target board rather than the bare IC because it is difficult to lay out because the target board effectively adds another layer, so I can get away with a two layer board.

 [ Invalid Attachment ]

Certainly some optimizations could be made.  Most of the footprints are 0805, and there are a handful of components on the back.  The project is attached. There are some things from your design that aren't in mine that could be added (mostly the second current transformer).

Dan
Title: Re: Next Gen DRSSTC
Post by: Hydron on June 20, 2018, 04:08:31 PM
I am looking at whether PSoC creator supports building for more than one target configuration. It does not look like it's something built in, so may be a case of copying source files between two separate projects (annoying, but doable).

I can also have a look at updating Netzpfuscher's (untested) PCB to use the same pinout, device etc as the dev board, but it may not be that simple on a 2-layer board with a QFN (also requires hot air to solder the chip, vs a QFP which is do-able with a reasonable iron).
Title: Re: Next Gen DRSSTC
Post by: profdc9 on June 20, 2018, 08:14:29 PM
Would it be possible to just change the same pins so that different parts would be used but the pins would be essentially the same?  There would be some flexibility to changing the pins of the devkit model but of course many pins are committed to things like capacitors, switches, and the two-wire port.

Dan
Title: Re: Next Gen DRSSTC
Post by: Hydron on June 20, 2018, 11:07:26 PM
It may be possible to do this, yes. I believe that the TQFP parts (in Netzpfuscher's PCB) are basically a superset of the QFNs on the dev board, so that any pin selection that works for the dev board can also work for a TQFP based PCB.

Unfortunately the PCBs out in the wild (those from when Steve Ward built his, Netzpfuscher's and one that I have) are designed around a pinout that can't be replicated with a dev board, so there'll always be a need for a couple of different configs. None of this is particularly hard, it's just annoying as someone has to muck about changing stuff for every code release.
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on June 22, 2018, 07:43:29 AM
I reorganized the code and found a relatively good solution for the different boards. I split the code in a common code base and the board specific files. The common code is linked in the board specific folders. The _QFN projects are for the dev board and the _TQFP for the classic boards.

If someone gives me the pinout of the dev board version I merge it to the git. I only need the ".cydwr" file. Or clone the new repository and make a pull request.

https://github.com/Netzpfuscher/UD3

common:
binary Binary files like the precompiled bootloader
ntshell Shell code
rtos FreeRTOS code
uart_ldr UART-Bootloader code
ud3core UD3 code
Title: Re: Next Gen DRSSTC
Post by: profdc9 on June 22, 2018, 09:41:05 AM
Here is what I have for the cydwr attached.  I also changed the clocks around as well.

Thanks,

Dan
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on July 17, 2018, 07:36:39 AM
There are a bunch of new features incoming. https://github.com/Netzpfuscher/UD3/tree/burst_mode


The Ethernet connects to the 8pin header on the UD3. I think Ethernet is a good choice. It is isolated, cheap and you don't need special Hardware. If you want to run a multi coil system, you can throw a switch between the coils and connect a fiber Ethernet to the computer. If I have the Firmware in a good state, I upload a release in binary form. I think it is much easier to flash a binary for someone who is no programmer ^^

We hit the 2m ^^




Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on August 17, 2018, 09:09:30 AM
I've made several bugfixes. Ethernet is working, Teslaterm is more stable.

Actually I'm working on the duty cycle limiter for the MIDI mode. My first proof of concept works relatively good. There are no more big current spikes if a very high MIDI-Note is playing.

Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on September 09, 2018, 07:59:44 PM
I've added a new synthesizer in the UD3. The new synthesizer "emulates" the famous SID chip. The UD3 interprets the music on a register level. The noise synthesis of the SID makes a very nice drum effects.
Title: Re: Next Gen DRSSTC
Post by: Uspring on September 10, 2018, 01:37:22 PM
Very neat  :)
There was a short discussion on 4hv a few years ago on tricks to enhance TC sounds.
http://4hv.org/e107_plugins/forum/forum_viewtopic.php?157570.0#post_157851
Title: Re: Next Gen DRSSTC
Post by: Hydron on September 10, 2018, 04:31:16 PM
Cool, new stuff to play with :)
Unfortunately I haven't had time to do much work on coiling recently, but I will be giving your new code a go when I get a chance. I'll also be in NZ again at the end of the year, so will have my large coil to play with too (I have a 75% finished UD3 board to install into it). On that note, Uspring - I'll be having another go at the toroid current measurements I promised and failed to do in April, this time I will have a lot more time to spare and hopefully won't injure my back trying to lift the coil down out of storage like I did in April!
Title: Re: Next Gen DRSSTC
Post by: Mads Barnkob on September 12, 2018, 08:56:06 AM
Great progress on the UD3 Netzpfuscher!

I will set it up as a goal for this winter to get a working UD3 with your software :)
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on September 13, 2018, 08:59:50 AM
One warning. The newest GIT-Version of the Dev-Board UD3 software has a messy pinout. I need to correct this before I merge it in the master branch. I use the dev-board for ethernet debugging so it is a little bit hackish. In general there is heavy work in progress ^^

I also work on a new PCB revision in Kicad with integrated Ethernet. Ethernet works so great and doesn't need special Hardware. I think it is better to go away from the expensive Altium ^^


Thanks to malte0811 the Teslaterm is growing. He added a scripting feature to automate the coil for show use.
In general the UD3 ist still fully functional with a normal VT100 Terminal.
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on November 07, 2018, 09:43:57 PM
I've made Teslaterm and the UD3 more user friendly with a settings form. I found some small bugs in Teslaterm and the UD3 and fixed these. The newest files are in the master branches:

https://github.com/Netzpfuscher/UD3
https://github.com/Netzpfuscher/Teslaterm

Title: Re: Next Gen DRSSTC
Post by: Hydron on November 07, 2018, 09:50:32 PM
Thanks! I'm about to order some boards to upgrade my big coil (in NZ) to a UD3 to use when I'm there over Xmas. Will take some pics/video and also some topload current waveforms to share.
Title: Re: Next Gen DRSSTC
Post by: plasmatree on March 25, 2019, 06:34:09 PM
Hello everybody and thanks already for this amazing work!
It has been >10y that I messed with tesla stuff, but somehow it's in my head again.  ::)
Looking at the different UD iterations using FPGAs seems obvious to me. Combined with the simplicity of this dev board... great!

I'm preparing to order the pcbs and was wondering if the plans for the Psoc5-Power (https://github.com/profdc9/DRSSTC-PCB-Pack) found in the pcb pack are still the most recent/recommended versions for this driver?
Should I consider to add or change something?

Greetings from Cologne,
Flo
Title: Re: Next Gen DRSSTC
Post by: profdc9 on March 25, 2019, 07:35:14 PM
Apparently there have been updates to the pinout that I have not incorporated into Psoc5-power yet, so you might want to hold off.  You don't need the board if you want to breadboard it.

I could update it if I get an updated pin list.  I haven't looked at the latest PsoC creator project lately to see what the new assignments are.  I think there is support for Ethernet now.

Dan
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on March 25, 2019, 08:07:10 PM
It should be possible to go back to the old pinout. I primarily changed it to make a simple connector cable to the W5500 board on my desk ^^
Perhaps I add a non development version with the dev kit to the UD3 project.
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on March 31, 2019, 08:54:25 PM
I've added a new experimental feature. A fuse emulation.

You set the maximum continuous current and the 10s limit from the breaker curve. The UD3 tries to limit the duty cycle to keep the fuse under 60% of the trip point. The gauge on the lowest right is the fuse (100% fuse tripped). The gauge in top of the "fuse" is the duty cycle limiter (higher is more limited).

If the controller can not keep the current low enough and the fuse reaches the 100% the UD3 shuts the coil down.

I think there is a lot to improve, but you can see what I'm trying to do.

Title: Re: Next Gen DRSSTC
Post by: Mads Barnkob on March 31, 2019, 09:51:28 PM
Very nice feature, I can really see that come in handy for shows where it would be good not to have a trip or any kind. Did you try it out with sparks and most interesting heavy ground strikes?
Title: Re: Next Gen DRSSTC
Post by: Netzpfuscher on April 01, 2019, 07:17:28 AM
No, this is the next step. The test in the video is only a static load test with a bunch of scrap metal in the primary.