What realistically should I be looking at for capacitor voltages?

I am under the impression that higher voltages are more efficient

Biggest advantage of high voltage is to minimize loss in parasitic wiring inductances.  However, too high has a mechanical down-side.  Single-layer launch inductors are most robust mechanically.  High voltage (low capacitance for same energy) could need a multi-layer coil to achieve desired resonant frequency.  My quarter shrinker does have that down-side of 2 layer coils being optimum:
    https://highvoltageforum.net/index.php?topic=1793.msg13556#msg13556
This is same cap as in my 345m/s disk launch.
If you are scaling an existing design, scale capacitance and voltage down by the same factor as coil geometry.  That way it will match coil inductance and optimum frequency.  Design capacitor array to match those voltage/capacitance specifications.

I'm not sure what kinds of capacitors are realistic to purchase from places like digikey or mauser, let alone ones likely to meet discharge timing needs.

Polypropylene capacitors are best.  (My ancient 14uF 20kV pulse capacitor is paper/oil/foil construction, 68kg for 2800kJ.  You can do better today.)  Look in particular at AC voltage rating of the capacitors.  For your low duty cycle, RMS current rating isn't critical.  Pulse current (sometimes specified as maximum dV/dt) will become important as frequency increases.  Capacitors can often be pushed beyond specifications with the tradeoff of reduced life expectancy.  Actual use time of capacitors is likely quite low for your launcher.  Reduced life may still be years of calendar time.

I am also under the impression that using many small capacitors could be better than less large capacitors, for discharge speed.

Generally true.  Large pulse-discharge capacitors are often made internally from smaller capacitors.

Do you have any ballpark ideas what would make sense, like what would be a practical goal and what would be an optimistic goal? (off the shelf versus scavenging abandoned missile silos and microwave factories)

Scale the large design, then see how many capacitors of what values are needed.  (Missile silos might be a source for larger pulse-discharge capacitors.  All I really know is such caps are export-controlled due to their usefulness for military equipment.  Sometimes show up in scrap auctions from nuclear weapons labs.)

I think I'm going to use thyristors by the way, and octocouplers from the arduino.

As I'd mentioned in one of the related posts, thyristors are not suitable.  Look at thyristor specifications, in particular at maximum dI/dt rating.  Will be far too low.  (Thyristors are bipolar devices.  Takes time for gate/base charge to spread across device.  Initial current is concentrated at gate connection of die.)  I do use TRIACs for my low-power launchers where both current and frequency are lower.  Arrays of small thyristors (TRIACs) might theoretically work.  I've tried that twice in two projects, both ending in failure.  Latest and by far the largest:
    https://highvoltageforum.net/index.php?topic=2230.msg16382#msg16382
Perhaps you'd have better luck.  Thyristors have another limitation in that they are slow to turn off.  At your likely frequencies, turn-off will not be possible.  Forces ring-down waveforms as with disk launchers.  Do such waveforms work with the design you are scaling down?

Have fun!

An additional confounding factor is this: "The desired exit slip S0 between excited wave in the barrel and the induced wave in the projectile is 0.005."

Exit slip will not be relevant with the scaling I've suggested.  You'll be discarding all the later stages of existing large design before scaling.  Discard everything past where projectile achieves 100m/s or whatever you want for a target velocity.  Then scale only what is left.  (Of course, you may want to aim a bit higher than your goal to account for actual construction issues.)

One last issue is scaling down the air gaps in these bigger designs leads to quite a close gap.

What matters is gap from coil ID to projectile OD.  Doesn't matter magnetically how much of that gap is air or tube or wire insulation, presuming none of the gap is conductive.  (Carbon isn't desirable for that reason, though depends on actual conductivity.  Carbon varies based on fabrication.)  Of course, aerodynamics will change with air gap vs tube wall thickness etc.  (If laminar flow, air drag energy loss would scale like resistive loss, by 1/100th.  I forget turbulent flow formulas at the moment.  I'd guess your air drag to be turbulent for most velocities of interest.)

Scaling issues with gap from coil copper ID to projectile OD isn't surprising.  However, that is a critical factor in efficiency, thus why gaps are as small as possible.

Basic physics is the same.  Changing magnetic field generates eddy currents in projectile.  I'm not familiar with any particular set of linear induction motor formulas and what geometry assumptions they apply to.  I'd expect calculated frequency to be similar. 

A linear motor approach makes sense of multiple poles fit along projectile length.  Since you are more familiar with those calculations, perhaps it does make sense to start there rather than my simplified single-pole model.  (I'm more familiar with basic physics, so tend to start with simple models.)  Either way, the hard part will be generating the necessary voltages and currents in the coils.  Much harder than control.  The simple single-pole pushing model I suggested simplifies that power part a bit since simple L/C ring-down waveforms work.  That's what a disk launcher generates just by discharging a capacitor into a coil.

Second hardest part may be sensing projectile location.  Can use separate detectors or inferred by coil waveforms.  Either way, that too will be more of a challenge than the processor or FPGA code to drive it.

My first instinct is that the most important thing to the outcome will be a properly timed system that is as optimized as possible for the most important variables.

To start, focus on power part of timing, not control part.  Each coil's capacitor needs to discharge (or ring down with coil inductance for early stages needing AC) fast enough.  That discharge speed and frequency will limit capacitor choices.  4kg may be hard with the discharge timing requirement.  Though 100m/s is certainly less challenging than 300m/s in that respect.  Electrolytic caps aren't an option for AC.

That's a very nice and clean build, good job!

Yes, looks great.

2x eupec BSM150GB120DL half bridge IGBT modules in full bridge configuration,

Long on-times of freewheeling designs can't survive quite as high peak current as for shorter on-times of typical DRSSTCs.  Also, unlike many bricks, diode thermal resistance is 2.5x higher than IGBT thermal resistance.  If using freewheeling extensively, diodes may limit current before IGBTs do.  I don't have any good info on how much current would be safe.  Hopefully you'll get other thoughts on this.

Are the TVS useful, or do they increase risk for blowing my bridge in the case they overload and fail short? I saw conflicting information while looking around. Is it better to put two in series for 880V?

Images suggest your TVS diode pairs are across Vbulk (high-side collector to low-side emitter).  If that is accurate, will not cause problems.  Not useful either as your bulk caps won't survive 880V.  Your bulk caps are plenty large enough to absorb energy from ring-down without over-voltage.

Is it an issue that one GDT ended up with one turn less than the other? I guess I will just have to scope the gate waveforms to check if there is a difference.

No issue.

Do I connect my MMC as parallel series strings, or as a set of parallel caps in series that results in a grid-like structure?

Parallel series strings is the most often used configuration that is proven to work, I'd stick with that.

Yes, more common, but either works.  My DRSSTC is half way between, grid within each section, but sections paralleled.  (I tune by changing MMC, so need to easily add or remove smaller sections.)

Do I need bleeder / balancing resistors for my MMC and if yes, what values / rating / type? Or is the 10k resistor across the bridge output enough?

It is known that UD1.3b driver was causing issues during the startup of each pulse due to residual charge on the MMC. This behaviour can be seen here:

I don't think that is an issue with newer drivers.  10kΩ 11W resistor across bridge output should help if it still is there to some degree.

However if you're going to use bleeder resistor, I would strongly advice to use resistors across MMC.  In case the resistors fails short circuit, it will destroy your bridge.

Power resistors rarely fail shorted.  AFAIK, carbon film resistors are the only type likely to fail towards low resistance.  Also, if resistors across MMC experience higher voltage, so must be higher value.  Useful for balancing MMC series strings, but not for discharging bridge output between enable pulses.

Do I need bleeder / balancing resistors for my MMC and if yes, what values / rating / type? Or is the 10k resistor across the bridge output enough?

My DRSSTC has ~470k resistors across each MMC capacitors, one for each parallel set of caps in grid configuration, just as a precaution.  Probably not necessary.  MMCs see AC, no intentional DC.  Only possible need I can dream up is if corona discharge from MMC internal connections has some DC component, such as one connection point emitting electrons into air better than it does positive ions.  I expect such an effect is too tiny to matter if it exists at all.

There is also the option of winding my secondary on a 160mm pipe instead of a 120mm one (same 0.3mm wire, same length). This would give me an aspect ratio of 1:4 and lower the frequency to ~80kHz, which would allow me to upgrade the IGBTs if I ever wanted (300A bricks). However looking at Mad's website, the resulting reactance of 65kOhm seems rather high compared to the recommended 50k-ish, and of course requires more space. Do you think it would be preferrable to go into that direction instead?

No personal experience here.  I have the impression from reading on this forum and a bit theoretical thinking that higher-impedance coils are better for freewheeling.

Have fun with your beautiful build!

I think I understand the issue now. The difference is that my current driver after the falling edge of enable will have one gate driver outputting high and other gate driver outputting low. This means there will be full input voltage across the GDT primary (not causing a short circuit thanks to the DC blocking capacitor). This also means that the secondaries of GDT will have nowhere to discharge.

However UD2.7 gate drivers will both output the same logic state (high) after the falling edge of enable.
This shorts GDT secondaries through the gate driver's high side PMOS through the voltage source it's being powered from to GND. Removing any charge from the Gates of power transistors.

Did I get that right?

Yes, with one tiny change.  UD2.7 gate drivers output high, so low side NMOS FETs are on.  Otherwise exactly correct.

Unfortunately I was in a rush to order new PCB as this coil needs to be finished soon. So the new driver PCB will use the "clamp" winding.

Clamp solution does leave one issue unresolved:  The DC blocking capacitor starts charged rather than at 0V.  Given lower IGBT current at start of enable, this start condition issue MIGHT not cause failures.

At the risk of providing too much information:  Your boards are trivial to patch.  Just use the driver chip enable pins instead of AND gate on input.  UD2.7 avoids using enable because that would leave driver chip outputs low.  Low driver outputs would turn on PMOS outputs, except that PMOS gate drive is AC-coupled.

I also don't see why it wouldn't work, though I'd be very careful about using pulse skipping or any other modulation that puts extra stress on the diodes (beyond the rundown phase they're going to be active during regardless).

I certainly agree with avoiding pulse skipping etc.  Even in normal operation, be careful of high enable pulse frequency.  Diode power capability is <4W average without heatsinking.  Depending on primary current at end of enable pulse, ring-down duration, and enable pulse frequency, wouldn't be too hard to exceed 4W.

Primary current was much lower for ~1.5ms or so before ramping up as usual, I think this is what helped to reduce branching.

Agree, that sounds likely.  Slower start helps reduce branching.  However, whatever is causing that change 1.5ms into ramp might be a cause of failure.  Only guess that comes to mind is that feedback isn't taking over from self-oscillation for initial 1.5ms under conditions of this test.

EDIT: Scope captures.

Yellow=Self oscillation output
Purple=primary current via CT
Blue=Primary output

Self oscillation is running around 781kHz before the coil turns on. Looks like that drops to 625kHz on startup and then all the way down to 490kHz at the halfway point.

Scope captures all look good.  Thank you for posting.

I find simulators very intimidating and frustrating as they rarely work for me. Either ICs are not doing what they should or the simulation breaks due to some random 100MV spike or there are some transients which make it impossible to extrapolate anything valuable.

Yes, simulating can be frustrating.  If you plan to work in analog electronics, simulating will likely be a necessary skill.  You'll learn techniques to minimize issues.  A few key ones below:
1) Use many initial condition statements (.ic statements).  Define reasonable voltages for key nodes.  Define initial inductor currents, especially if initial voltages would cause inductor current.  Usually setting inductor currents to 0 works well.  Sometimes non-zero current is good for rapid starting of oscillators.
2) Use as simple device models as will suffice.  LTSpice provides a couple basic opamp models for example, or use a voltage controlled voltage source.  If opamp bandwidth, drive current, etc. aren't critical to circuit, use simple models.  Use built-in LVDMOS model rather than fancier models from manufacturers.  BTW, I simulate with LVDMOS FETs even if actual circuit is IGBT.  I find IGBT models are often problematic.
2a) If details are critical for one or two devices, use manufacturer models for just those devices.
3) If simulation has issues after beginning, sometimes setting smaller time step helps.  Does slow down simulation, however.  Automatic dynamic time steps are usually fine.
4) Label all nodes (wires), or at least all that are being probed.  Makes read/communicating simulation results clearer.
5) Add some realistic parasitic series and parallel resistance to inductors.  Ideal (undamped) inductors sometimes cause issues.

Your posted simulation looks reasonable, though node labels and .ic statements will help.  I can't tell what nodes are being probed (nodes 4 and 7) without labels.  Probed voltage looks odd for any pair of nodes I can think of.  Also, add a defined number of pulses so pulses train ends to simulate end of enable time.  That enable end is the issue you want to study if I understand above post.  Also, I'd add GDT input parallel snubbing to make sure GDT primary matches real circuit.