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Messages - davekni

Pages: 1 2 [3] 4 5 ... 23
41
Yes, I understand that you increased primary inductance.  I was just suggesting to do that with additional turns rather than closer spacing.

Undershoot on the gate waveform is the peak negative spike immediately after each falling edge.  The diode bypasses the resistor for falling edges only, reducing the damping.  GDT leakage inductance and gate capacitance will combine to make the resonant undershoot spike without the series resistor damping.

Perhaps, if the primary control logic is tied to primary voltage (so no regulatory safety requirements) and the primary voltage isn't too high, they got away with enamel insulation.  There are different grades of enamel, including multi-layer coatings.

One more thought on the half-bridge output ringing in some of your previous waveforms:  Perhaps that was caused by brief cross-conduction, where one FET turned on slightly before the other turned off.  Diodes across the gate series resistors are to insure no cross-conduction (no shoot-through).  Or, the version with a series resistor on the GDT primary and none at the gates works well as long as the GDT leakage inductance (and wiring inductance from GDT to gates) is low enough.  Then no diodes are needed.  That's the version I use more often for FET H-Bridges and half-bridges.  (IGBTs need a bit more delay to prevent cross-conduction, so the gate resistor and parallel diode option is better for driving IGBTs.)

42
The enamel-insulated GDT was likely for a low-voltage application such as synchronous rectification on the secondary side of the supply.

Two concerns with using the non-1:1 GDT:  One, the leakage inductance is almost certainly higher since the windings can't be paired as well.  That will add more ring to your gate waveforms.  Second, and likely more important, is the added load on your gate drive ICs.  The load they see goes as the square of the turns ratio.  So a 1.5:1 ratio will more than double load on your driver chips.  Check temperature carefully if going that route.

Your two gray 1uF caps are your snubbers.  Larger caps will help as long as wiring is short, especially with your long wires to the electrolytic bulk caps.  It can also help to have a cap across all of VBus (across the pair of 1uF caps), from bottom source to upper drain.  You can cut inductance in half by adding new snubber caps on the other side of the FETs, so they have separate short wires.  Larger snubber caps may make your current waveform closer to the expected triangle wave, as both VBus and the center-tap will be closer to DC (less ripple voltage).

Reducing primary area is decreasing coupling, but increasing primary inductance.  You'll likely get better performance by keeping the primary spread out, and adding a turn or two to get higher inductance.  It's the higher inductance that is reducing your primary current.

When using gate resistors on the secondary of the GDT, parallel diodes are recommended.  It will make gate-drive undershoot higher, but be more certain to avoid shoot-through (simultaneous conduction of both FETs).  Since your FETs have higher max Vgs, the undershoot shouldn't be an issue.  If undershoot is too much, either add a bit of series resistance to the GDT primary or a bit in series with each diode.

There's some interesting ~20kHz ripple on your half-bridge output.  Where is the scope probe grounded for that measurement?

43
My preference is to ground the driver circuit.  That way if any stray fields attempt to charge the driver circuit, it won't cause any breakdown of GDT insulation.

44
Size of the capacitors at the half-bridge depend on how long wiring is from the electrolytic capacitors.  If it is all close with low-inductance connections (ideally copper planes), then small film caps work fine.  With spread-out wiring and its associated inductance, then the local film capacitors need to handle more of the current.

Scoping works fine as long as you are using a transformer for feeding VBus (the half-bridge power, from lower FET source to upper FET drain), then scoping is easy.  Ground the scope probe to the lower FET source.  Scope the upper FET drain, and then scope the junction between the two 1uF caps.  If powered directly from line voltage, then don't ground a scope probe to any of the half-bridge circuitry!  Ideally the voltage measured at the upper FET drain (voltage across both 1uF caps), and the voltage to the center point between 1uF caps, show mostly a DC waveform, with ripple say 20% or less of the DC value.

For DRSSTCs, the difference between clean and ringing H-Bridge output waveforms is usually proper phase lead.  If the H-Bridge switches just before current zero-crossing, the switching is smooth.  If after current zero-crossing, there's much more ringing.  SSTC designs generally switch well after current zero-crossing, so I suspect ringing is common.  Low inductance between the FETs and 1uF caps will help that ringing.  Higher gate drive resistance also helps by slowing down switching, but at the expense of lower efficiency (more FET power dissipation).

Hard to tell from the picture, but yes, if your new GDT is just enamel insulation, use it only at low voltage.

45
The gate drive waveform depends on where it is being scoped and where series resistors (and diodes if included) are connected.  If scoped on the drive side of any gate series resistors, then the step will not show up or be much smaller.

The distorted sine wave is a bit odd.  Part of it could be that the 1uF caps on the half-bridge are too low value to make VBus close to DC.  You could scope VBus at the half-bridge to see.  Another part may be the current transformer.  An old large UPC may have ran at 5-10kHz, so the CT may not be good at 200kHz.

It's also that few people measure SSTC primary current.  Most primary current plots here are for DRSSTCs.  I'd expect SSTC primary current to be closer to a triangle wave.  Perhaps your "distorted sine wave" is closer to a triangle wave modified by the two factors I mentioned above.  SSTC primaries are intended to not be resonant.  They will have a resonant frequency due to the coupling capacitor (4.7uF in your case), but that should be well below operational frequency.  So, if the caps are large compared to operating frequency, then the half-bridge is feeding a square wave into an inductor (primary coil).  Inductor current is the integral of voltage.  Integral of a square wave is a triangle wave.  Secondary resonance will change that shape some.  In your existing setup, coupling is low, so secondary current will have little effect on primary current.

For measuring current by voltage across the 4.7uF cap, it's the same as measuring voltage across the series resistor using two scope probes and subtracting the result.  The voltage across the cap will be larger, so easier to pick out from noise.

46
Yes, the primary drive ringing is likely due to remaining wiring inductance from the two FETs to the center-tapped VBus caps.  I presume those are the black caps adjacent the heat sink - the end of one being visible.

SSTC resonance is just the secondary.  Reducing the primary turn count lowers primary-secondary coupling, raising the secondary inductance (with primary "shorted").  SSTC primary drive is low impedance, so effectively shorted for the sake of measuring or calculating secondary resonant frequency.  However, 290kHz to 250kHz is more shift than I would expect.  Anyone else have more experience with this?

Have you tried using antenna feedback yet without the signal generator?  If the secondary resonance is high-Q, you may not have managed to hit it precisely enough with a signal generator, or managed to manually track the frequency shift as sparks develop.

Another experiment to try is spreading out the primary coil farther.  Make the primary taller by adding space between each turn.  Or wind the primary with two or three wires in parallel.  That spreads the primary out by a factor of two or three and lowers winding resistance by the same factor.  Either way, this increases coupling factor for a given primary winding count.  It will also decrease primary inductance a bit.

47
Sorry about your hard failure.  What duty cycle were you running at the time?  Tests at low repetition rates and short enable pulse widths are unlikely to fail due to hard-switching with a good low-inductance layout as you now have.  (High VBus inductance can make large voltage rings at hard-switching points which over-voltage IGBTs.  With you layout that shouldn't be an issue.  The other problem with hard switching is power dissipation.  That would cause damage only with longer enable pulses.)  So, I'm wondering if there's any possible malfunction of the gate-drive circuitry.  Any unintended feedback from wiring inductance etc. that could have created a high-frequency gate signal or a partial-voltage gate signal or a signal with overlapping gate drive (negative dead time) could cause frying.

The reason for a second measurement-only current transformer is that your phase-lead circuit isn't a pure resistive load for your feedback CT.  Measuring voltage on the existing current transformer isn't an accurate measure of current due to the complex load impedance.

48
Much improved layout!  Especially good to see the two 1uF caps on VBus adjacent the half-bridge FETs.

Your gate drive waveforms look fine.  Mads explained the step well.  It is normal.

That current transformer may be good.  Most current transformers are for line-frequency use, but that one looks more like something from a switching power supply.  There is no way to know for sure without specifications or measuring it yourself.

Yes, differential measurements of small signals on top of a large common-mode signal is difficult.  To make the differential signal larger, I'd suggest measuring voltage drop across the primary coil series cap, the black cap at the back of your pictures.  (What value is that cap?)  That will give you the time-integral of current (current with 90 degree phase lag).  Knowing frequency and capacitance allows calculating the primary coil current.

Primary-to-secondary coupling factor looks very low for an SSTC.  I'd suggest spreading out the primary windings (space between each turn) and perhaps adding another turn or two.  Most SSTC designs I see here have the primary covering 20-50% of the height of the secondary.  Others here with more SSTC experience may have more precise suggestions.  Many have a piece of pipe or other insulating cylinder as a primary winding form to insulate it from the secondary, especially important at the upper end of the primary winding where secondary voltage is significant.  The primary winding form usually extends a bit above the top end of the primary to avoid arcs around the top of the form.

49
Yes, I also find minimum on-time helpful.  Besides enforcing a minimum, I'm making pulse width proportional to sqrt(volume).  That subjectively seems to help, but I don't have good comparisons.  At least for pulses towards the short end, current is growing roughly linearly with time, so total energy is growing as time squared.  Sqrt() undoes that square relationship.  For longer pulses, primary current envelope is more complex, especially with the beat between primary and secondary frequencies.  The sqrt() function isn't a match for long pulses.  On my coil it works out well, however, reducing excessively-long pulses.

The sqrt() function is applied after merging or separating pulses that are too close.

I'd love to make a more accurate translation from instantaneous note volume (including any other notes outputting a pulse at the same) to pulse width.  The mapping would need to be quite complex, perhaps too complex and variable to be within reason.  Spark behavior depends heavily on pulse history - how much of an ionized air path is built up.  Relevant history appears to go back much farther than I was guessing.  And, of course, ground strikes make a significant difference too.  My hope was to set up a microphone and measure sound impulse energy vs. pulse width.  The long history makes that impractical.  If only one or two pulses of history matter, could capture that before echos interfere.  Anyone have access to an an-echoic chamber for coil testing? :)

50
In an ideal world, the only power dissipation is in sparks from the secondary top.  If sparks are short and weak, they aren't dissipating much power.  Of course, in this real world, there are other power losses, in FETs and winding resistance.  Sparks should still be dominant for power dissipation.

Presuming sparks from the top are minimal, low coupling from primary to secondary is my first guess.  Could also be too high a primary impedance (too high inductance for the frequency), causing primary current to be low.  One way to measure primary current is by voltage across C9 in the SSTCIII bridge schematic.  Knowing frequency and capacitance and voltage allows calculating current.  Double to get primary coil current, since half goes through C8 and half through C9.

Finally, if the half-bridge phase is too far off from secondary voltage phase, drive will be inefficient.  (Another way to say this, if phase is off, oscillation frequency will not be centered on the secondary resonant frequency, so secondary voltage will be low.)

A few pictures would be helpful, showing your primary and secondary, half-bridge wiring, and gate drive transformer.  If there is still too much parasitic wiring inductance, that could be causing the circuit to misbehave.

BTW, placing non-identical transformers in series is not a problem, as long as the load current isn't more than the rating of the transformer with the lower rating.  Of course, short-term higher current is usually fine for hobby use.  Paralleling non-identical transformers is more likely to cause issues, as their output voltages may not be identical.

51
For an SSTC at 240kHz, FETs would be appropriate for the half-bridge driving the primary coil, not IGBTs.  SSTC circuits are not zero-current switching.  Rather SSTC circuits switch at high primary current.  IGBT switching losses would be too high.  Also, IGBTs are designed for 15Vge.  This SSTCIII circuit provides 12V gate drive.  (I did swap IGBTs for FETs in one of my designs with 12V gate drive, but first checked my IGBT parts to see that they functioned well there.  It was a zero-current switching circuit, so didn't have switching loss issues.)

What half-bridge parts are you using now for low-voltage testing?  Are they IRFP460 as in Mads SSTCIII?

How is performance using your 60V 5A bench supply?  That's enough power for some reasonable sparks.

If you are already using IRG4PF50WD IGBTs, keep the enable pulse duty cycle low (short on times and long off times) and check IGBT case temperature.  Those particular parts look like they may work OK at 12Vge, although spec'ed for 15Vge as is normal for IGBTs.

52
As klugesmith pointed out, calculate what 10nH of inductance of your 0.01 ohm resistor will do to phase.  I suspect resistor inductance is at least that much, more likely 20-30nH.

If you have an extra of your CT cores, make one more single-stage CT of say 40:1 and use a low-inductance 10 ohm burden resistor.  20-30nH will have much less effect on 10 ohms than it does on 0.01 ohms.

53
Electronic Circuits / Re: Vacuum capacitor circuit advice
« on: June 06, 2020, 08:19:44 PM »
You could purchase a regulated lab supply with adjustable current, or look up constant-current circuits.  But I'd suggest not trying to replicate a worthless patent.

54
58 degrees seems quite high.  The current-sense transformers shouldn't be making that much difference, especially at low power where core saturation isn't an issue.

Are you using the same phase-lead circuit shared in your previous thread, with 100-ohm input resistor?  One difference relative to signal-generator testing is that the signal generator output impedance is likely 50 ohms, not a current source.  50 ohms in parallel with the 100 ohm input resistor makes 33 ohms net.  Your circuit will add a bit more phase lead with that lower input impedance.  For a test, try paralleling 50 ohms across the input along with your CT output.

You mentioned that your phase-lead circuit matched delays to the IGBT gate signals.  The IGBTs themselves add more delay, which should be compensated with additional phase-lead.  The goal is to have IGBT outputs switch slightly before current zero-crossing.

Can you post a picture of your current transformer and of scope traces showing phase of signals relative to your current-sampling resistor?  Signals to probe (along with current-sensing resistor) are current-transformer output, gate drive, and IGBT (H-Bridge) outputs.

How are you scoping the current-sampling resistor?  Do you have a differential scope probe?  If I recall correctly, this is a full H-Bridge design, so the primary circuit has no grounded location to place a current-sampling resistor.

55
The UCC chips will work correctly with high output levels for the off state.  They are not stressed in this condition.

The germanium diodes on the antenna input have some small leakage current.  If the two diodes are exactly matched, the voltage would be at 2.5Vdc.  The scope probe or meter used to measure this voltage will pull it down with 10meg (or whatever meter input impedance you have), to 1.1V in your case.  If your antenna signal is weak, probing this node might disrupt operation.

56
Yes, voltage drop variations are a concern, but probably not unreasonable for your build.  Your good layout will minimize inductive drops.  Resistive drops are likely within reason too.  Driving the gates with +-20V allows for +-5V variation while maintaining at least 15Vge.

If you want to be more sure of Vge, use multiple GDT windings, with each winding driving a smaller set of IGBTs.  I'd posted somewhere back in this thread about that option.  Even 28 winding pairs, one per IGBT, with all primaries paralleled isn't unreasonable.  (The other half of each twisted pair winding are all paralleled for the GDT primary.)

Ideal way to find gate resistor power is with simulation.  For a crude estimate, calculate the energy stored in the gate capacitance, then presume that energy is dissipated in the resistor every cycle.  (Worst-case, it could be 4 times as high, since the gate is swinging twice the voltage, from -20V to +20V.)

On an unrelated note, attaching TO247 packages to heat sinks with their "mounting" hole is not always effective for heat sinking.  The attachment force isn't where the die is located.  Most commercial designs use some form of clamp or spring clip applying force over the die, roughly 1/2 way from the leads to hole.  Depending on how compliant and thermally conductive the pads are and how consistent screw tightening torque is, this may or may not be a big issue.  All it takes is one hot (poorly heat sinked) part to fry shorted, and the failure will cascade.  (I think the mounting holes are there for historical reasons.  Designs from 50 years ago used the holes, until engineers figured out that thermal performance was unreliable that way.)

57
I liked the bit showing electrostaticly-induced waves in the oil.  Obvious effect in hind sight, but something I hadn't thought about before.

I'm surprised the diodes survive the current spikes during discharge.  I wonder how long the diodes and caps will survive.  I've used those Chinese 20kV diodes, but not with sudden discharge.  I've also found those cheap Z5U HV caps to fail with repeated spark discharges without ballast.

58
Adding extra turns is essentially the same as adding a series inductor.  It's simpler, but a bit more tricky to insure staying within limits for ZVS oscillation.  Sorry to hear of the frying event.  Encouraging that you have a likely cause.

If you can afford an inexpensive scope, that makes a dramatic difference in debugging and understanding circuit behavior.  Something like Hantek DSO5102P for $250 new on EBay from several stores.  I have the slightly more expensive version that includes a signal generator.  There are USB scopes that use a host computer for display and control, some a bit less expensive.  There are also old used scopes for yet less.

Keep learning and having fun!

59
Voltage Multipliers / Re: Russian voltage multiplicator stacking
« on: May 31, 2020, 07:32:32 PM »
Yes, as ritaismyconscience said, grounding V will short-circuit the AC input.  Doesn't matter what loading is after that.

Yes, I presume F is for focus.  I'm just guessing that the Russian TV needed some negative voltage as well.  I've seen some TVs with two separate positive focus voltages, so there are clearly different options in CRT electron gun designs.  Perhaps they bias the cathode negative, or have some other negative electrode(s).  This is just guessing.  I have no documentation suggesting how the V terminal was used.

If you added an external series capacitor to the AC input, then V could be grounded, and it would become a 6x multiplier.  However, I don't know if the first (lowest) internal capacitor could handle 2x voltage.  It normally sees only 1x voltage, half as much as the other 4 capacitors.

60
Nail polish is a good idea.  Make sure the board edge is clean so it adheres well.  Coating doesn't help if not bonded to the bare board between copper.  I'd use clear polish, although colors are probably fine, presuming none of the color pigments are conductive.

What is your line voltage?  I'd thought you were in a 230V part of the world.  Peak doubled would be 650V, too high for your IGBTs.  If 120V line, the peak doubled is 340V, so should be good.

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