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Topics - davekni

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Inspired by Phoenix' huge ferrite transformer arcs:
    https://highvoltageforum.net/index.php?topic=433.msg2609#msg2609
I decided to make a small version powered from standard US 120V outlet.  It uses a ZVS Royer oscillator directly from the rectified line voltage input, driving an 8-turn center-tapped winding on one E80 core half.  The other core half has 102 turns.  Halves joined with 0.55mm spacing for K=0.83 coupling factor.  K < 0.86 allows the oscillator to run over the full range of arc load resistance, at higher frequency under lower-impedance load.







Most of the work involved exploring how to get the ZVS oscillator to start cleanly without a huge inrush current spike, which is followed by an oscillator voltage spike due to the large energy stored in the input inductor (L4 in the following schematic).  My final solution was to bypass the power switch with a resistor R2 (actually a small incandescent light bulb).  This starts the oscillator at low power.  Once oscillating, it transitions to high power more smoothly.



Switch S1 is actually an electronic switch with isolated LV control and over-current shutdown.  Internal details of S1 aren't shown here.

Output voltage before an arc forms is +-5.5kV.  Short-circuit current (very short initial arc) is +-2.7A.  Below is a scope-capture of voltage (1kV/div with 1000x probe) and current (1A/div using 10ohm low-inductance sense resistor).  This capture is at the end of a rising arc, just as it is breaking up, where power is highest.  Second image is a zoom into the middle of the first.




To get a longer time view of arc characteristics, I switched rectified sensing.  Below are DC signals of average current and voltage.  Full-wave rectification with low-pass filtering, but no cap at the diodes (to avoid getting peak voltage).  Voltage is 450/div, or about 500V/div RMS if sine-wave is assumed.  Current is 0.5A/div average, or about 0.56A/div RMS for a sine wave.  First image is a 2-second overview, followed by two zoom-ins.





At the left voltage goes off-screen for 12ms, from turn-on until the initial arc strike.  There's much more instability in arc impedance than I'd expected, as the arc momentarily sticks to rough spots (or whatever surface characteristics make a favorable arc point).  The final arc break-up at the end of the scope capture triggers my DC input over-current limit.  Voltage doesn't drop to 0 because of the switch bypass resistor R2.

The 8ms period modulation of the current and voltage waveforms is due to rectified 60Hz line power.  The "470uF", which measures 415uF, input cap doesn't hold voltage well between line half-cycles.  That's intentional to keep power factor somewhat reasonable.  I'd initially started with just 3uF to filter HF components.  However, the arc goes out much too easily without some current flowing continuously.  Adding the 415uF DC bus capacitor made a big improvement in overall performance.

Finally, a couple videos:
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2
Here's my first attempt at documenting a project.  It is my first DRSSTC - just complete enough to run, but with much enhancement work planned for the next couple years.  A few videos of operation, at the Portland (Oregon, USA) Mini-Maker Faire, and a couple in my back yard two weeks earlier :
   
   
   
   
   

Don't have a good assembled picture of the coil, but here's the parts:
   

MMC, with lots of room for planned expansion:
   

H-Bridge with 0.1mm x 100mm copper foil output leads.  E80-core current transformer is hidden under bump in output foil at right end.  Purple clip in the upper left quadrant is a crude optical probe (LED and resistor into plastic fiber) monitoring one of the high-side gate drive signals.  The pairs of TO220 FETs are the gate drives on floating 18.5V supplies, one PFET and one NFET per H-Bridge switch, driving 10 paralleled STGW60H65DRF IGBTs (hiding under the aluminum bar clamps):
   
The bulk cap array is under the H-Bridge, so not visible.  96 x "470" uF 450V.

Control circuit - in an aluminum-foil lined cardboard box at this point:
   

4-turn primary coil made of 200 strands of 27AWG wire.  Inner turn gets warm at 3kW.  Will need finer litz and/or cooling air directed that way to get 10kW eventually:
   

Bulk-cap circuit:
   

Main oscillator simulation schematic, using voltage-controlled-voltage-sources for gate drive, and FETs  for the H-Bridge because they simulate faster.  The center lower part is mostly a comparator made of discrete TO92 FETs, from M3 on the left through M10 and M11 on the right.  Nodes "vn" and "vp" are the inputs and nodes "v2" and "v3" are the true and inverted outputs.  R2, R3, R4, R7, R11, and C10 are the relevant feedback around the comparator.  No one would want to copy my comparator itself.
     

Current limit is also a bit unusual.  It is fed with a voltage-transformer (L1 and L2) from the oscillator current transformer output.  (My current transformer is 40:1 first-stage, then two 25:2 second stages.  However, one of the second stage outputs is for scoping only.)  The current limit circuit includes not only an immediate shutdown at 3500A peak (2600A in this initial version), but also simulation of the IGBT thermal transient response (C1 and C2 and associated resistors).  That way repeated long bursts will get aborted even if they don't reach 2600A.  (So far, the current limit trips only in my initial primary-only testing, not in real use so far.)
     

Finally, here's a hint of where I hope to go.  This is a sketch of a small part of what will be an array of ~500 TRIACs to switch in more primary tank capacitance as each arc grows.  My goal is to make it behave more like a QCW coil, but hopefully even better with a reverse-chirp in primary frequency to match the secondary frequency change with arc growth:
     

Before this fancy reverse-chirp attempt, I need to improve my MIDI interrupter setup, at least for next year's Maker Faire.  Also need to redo the primary tank circuit connections - going to use spade connectors instead of many paralleled 0.025" square pin connectors - that come apart too easily.  Going to explore detection of power arcs and termination of the drive enable pulse once a power arc forms.  That should make overall operation more efficient.

Hopefully I have the jpg attachments figured out now.

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