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Messages - black.yang
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1
« on: July 05, 2023, 09:48:21 AM »
I'm sorry, he just did simulation and didn't actually build it. I saw a 2.6 meter QCWDRSSTC on a forum in China, and the following is the image provided by the translation software. 2.6m is great. Nice images. More reasonable for an actual coil than 5m. BTW, my ceiling is only 1.52m above my QCW breakout point. A few of my slightly-curved arcs did not quite hit my ceiling and extended horizontally for ~2m. They were probably close to 2.6m total, but I don't have any measurements.
Hi dave, I'm glad my friend put our discussion here. After reading the above discussion, there are some differences between my ideas and the screenshots displayed. The idea behind all of this is that Caojin and I are fantasizing about a QCW with an arc length of 5M and discussing the technical solutions needed to complete it. High coupling can turn QCW into a traditional transformer, and the ratio of primary and secondary coils can become an important factor affecting the voltage ratio. But when the arc needs to become longer, higher voltage gain Q is also needed to achieve the energy requirements brought about by the continuous growth of the arc. At this point, make the frequency of the primary and secondary coils consistent. It seems beneficial. I am considering using some method (like adjustable inductor)to achieve tuning, if necessary. This method also has the advantage of locking the QCW at the "upper pole" or "lower pole", and achieving soft switching at the same time. Compared to the "leader pulse" achieved through the intervention of the driving signal, it has certain advantages.
2
« on: June 10, 2022, 08:20:37 AM »
I refer to many posts here, and generally use two methods: Two other options to consider. One is modifying UD2.7 to be self-oscillating at or above upper-pole frequency as in this thread: https://highvoltageforum.net/index.php?topic=1914.msg14912#msg14912 Another option is to use a PLL design instead of UD2.7.
However, in fact, by analyzing the FFT (I (L1)) channel current, it is still found that there is a peak at the lower frequency point, that is, the existence of the pilot pulse does not solve this problem Looks like your next post demonstrates (accurately) that this can work. Energy at lower pole likely decays over the simulation time. Perhaps a time-window on FFT would show this. Also, if you want to reduce lower-pole energy, start with a half-width pulse (quarter-cycle) to avoid a net DC step at the start of operation.
I prefer to have a more stable method to track the upper pole, and specify the working state of ud2.7 through the unique characteristics of the upper pole, such as phase, gain, etc., so do you have any good ideas? Or have you ever done research in this field? I will implement these ideas in my CPLD driver circuit PLL designs are probably the most common solution here, if you want to insure no pole hopping. As USpring showed in some post, at heavy-enough arc loading it is possible for the upper pole to no longer be capable of ZCS operation. In that case the only options are to permit non-ZCS or terminate the enable pulse.
Impressive use of LTSpice! I learned a couple constructs from your posts.
Hi Dave, Thank you for the link you sent me. I got inspiration from it. By designing the positive feedback self oscillation of the comparator, the pulse guidance function can be well realized on ud2.7, because the feedback strength will cover the start pulse I reset my LTSpice simulation settings to avoid the step excitation to the system. When the system operates at the up / down frequency pole, the energy of the other pole is obviously weak, which makes me sure that the guidance pulse is working As for PLL, I think it may be a available to working but not optimal solution. Digital phase locked loop (DPLL) or analog phase locked loop need to lock the frequency / phase through k-mode counter or phase detector through LPF. This process takes a certain time. The frequency of QCW TC will change with the influence of arc length, which may inevitably delay the loop, and hard switching will occur. But in most cases, DPLL is a good choice. Maybe I am too cautious I think I will try to use simple combinatorial logic and use as few resources as possible to avoid FB working at the lower frequency pole. I will show the results in this post.
3
« on: June 08, 2022, 08:28:32 AM »
Next, I designed a circuit diagram to guide the pulse. After running in LTSpice, I can see that it works well. In the same QCW TC, through 5 pilot pulses, the coil can reach the perfect soft switching ZVZCS state at the upper and lower poles at the same time. It also verifies the frequency domain simulation Bode diagram (0 phase intersects 1 and 3 poles). In the simulation system, the strategy of guiding pulses is undoubtedly feasible. (if you know the person who put forward this idea, please help me pay tribute.) But my doubt is that if there is bistability in QCW TC, once there is some possible disturbance (arc shot on the ground, environmental change), there is the possibility of unstable tracking, and the arc capacitance of QCW TC will continue to increase, thus destroying the state of tracking at the upper pole. Is there a design that allows the circuit to operate stably in a certain frequency range? I consider implementing this function in CPLD. What I can think of at present is to generate a counter with fixed overflow time through Verilog, and the rising and falling edges of FB signal (TC driving square wave) will constantly reset this counter. Once it is lower than the upper pole frequency, the interrupt signal will be reset and TC will be closed. However, this method is complex and may cause failure when the arc is long I prefer to have a more stable method to track the upper pole, and specify the working state of ud2.7 through the unique characteristics of the upper pole, such as phase, gain, etc., so do you have any good ideas? Or have you ever done research in this field? I will implement these ideas in my CPLD driver circuit
4
« on: June 08, 2022, 08:01:24 AM »
Hi Everyone, Since I manufactured my first QCW in 2017, a lot has happened in recent years. But fortunately, I have been idle in my work recently, and I began to think about the "pole" operation of QCW Generally speaking, ud2.7 will be locked at the upper pole of QCW to minimize the impact of arc parasitic capacitance. I refer to many posts here, and generally use two methods: 1:Adjust the primary coil detuning to a higher frequency to approach the upper frequency pole 2:Use "several startup pulses" to guide ud2.7 to work at the upper pole frequency Based on the above two methods, I used LTSpice to do simulation content before actual production, and I will show it here. Above, I simulated an ordinary QCW, and can see its primary coil current gain and phase Bode diagram. In the diagram, I marked the intersection of phase 1, 2 and 3 which are 0, of which the gain of intersection 1 and 3 is (lower&upper pole)the largest at the same time, and the intersection 2 will not be captured by ud2.7 due to its small gain. So I began to wonder. Because Bode diagram can describe the response of linear time invariant system, we can reasonably judge that ud2.7 will work at the upper and lower frequency poles indefinitely whenever there is disturbance Next, I will perform time domain simulation on the same circuit (some parameters are adjusted to be closer to the reality) to verify this result. I set the parameter scanning to give QCW 1-10 pulses of excitation signal (432khz) working at the upper frequency pole. Normally, ud2.7 can be locked at the upper frequency point by doing this. However, in fact, by analyzing the FFT (I (L1)) channel current, it is still found that there is a peak at the lower frequency point, that is, the existence of the pilot pulse does not solve this problem
5
« on: February 15, 2019, 08:54:20 AM »
You can see what you want from this page. https://4hv.org/e107_plugins/forum/forum_viewtopic.php?p=1&id=179388#post-179400In fact, there is only one GDT in the original design. In order to ensure magnetic balance, when the current over the threshold, a resonance period width will be skipped on the GDT. So it is more suitable to call it "skipping cycle". A ramp signal input port is reserved on the circuit board. It has been tested that it can be used to operate QCW mode, but the test effect is mediocre and the arc does not look straight.
6
« on: February 13, 2019, 06:57:22 PM »
7
« on: February 13, 2019, 06:55:42 PM »
Hello, everyone. Recently, many friends mail to me to find to Yunbao driver's manual. Yunbao was originally designed by me and later shared its code with some Chinese form enthusiasts. So project was fork and made it a cheap driver for hobbyists. I got a product user manual from the fork designer, Unfortunately, at this version it is described in Chinese. Fortunately, the ports in the picture are described in English, you may need to use Google Translate to help you understand more detail. But it's better than nothing. enjoy it!
8
« on: January 10, 2019, 02:11:58 AM »
Hi black.yang and welcome to HVF
Impressive coils, outstanding work on the digital driver and great to have someone on the forum that understands Chinese, as you could see in the aliexpress driver thread, we do have a hard time when all we have available is google translate and sometimes a lot of text comes on pictures.
Please do make a thread or two to show some of your best coils, I took a look at your youku account (Chinese pendant to youtube?) and you have a good variety of work there.
Thanks for your warm welcome. I think I may be able to help translate the Chinese I can, even though I sometimes rely on Google. In the future, I will gradually update my work in the forum posts.
9
« on: January 06, 2019, 08:34:46 AM »
With the AE 1.3 driver you can use a matching fiber transmitter diode connected to the steve ward interrupter, if there is issues with polarity of the signal, you can either omit or use an extra hex-schmitt gate that is most likely available on the board as all are not used.
UD1.3b tries to do ZCS switching from the feedback transformer, but it does not have phase-lead compensation as UD2.1 does. This is really only necessary if you plan to push a lot of current through bricks or pushing something else above its limits. F.ex. I never had problems in my DRSSTC1 with UD1.3b: http://kaizerpowerelectronics.dk/tesla-coils/kaizer-drsstc-i/
DO NOT use RCA or coaxial cable instead of fiber optic cable! You will only make problems for yourself in two areas. 1. noise injection into the interrupter and 2. you are no longer galvanic isolated from the mains powered inverter / high voltage side.
I found a matching fiber optic diode https://bit.ly/2SWaCAG but it seems kinda exotic, with no tutorials or info on how to use it. I couldn't find the appropriate fiber optic cable, too. Any other options?
The reason I liked the driver in my OP was because it already comes with it's own fiber optic controller and that sort of jazz. Can I use that for my first DRSSTC?
On the IGBT side of things, is this Chinese one any good? https://bit.ly/2RJ0pGh My guess is probably not, but I am not sure why. What are the odds of it working fine? I am working from a limited budget, so I am stuck with Ali Express.
In fact, it uses an audio fiber head. Carrier-borne Manchester coding requiring a certain frequency Decoding interrupt signal in CPLD Logic Description It can be used safely.
10
« on: January 06, 2019, 08:20:21 AM »
Hi, everyone. I am a 24-year-old Tesla coil hobbyist from Wuhan, China. My job is Chip Technology Support Engineer. I have 11 years of Tesla Coil hobby experience. The first Tesla coil was made by winding the coil with a mineral water bottle. The arc was only 2 cm. At present, I have done DRSSTC, QCWDRSSTC and some CLASSE design experience. I just finished the design of "Yunbao" jump pulse driver the year before last, see it https://4hv.org/e107_plugins/forum/forum_viewtopic.php?id=179388This is part of my work page. https://i.youku.com/i/UMTEyMDQ1MzYw/videos?spm=a2hzp.8244740.0.0‘Yunbao’pulse skipping driver Recently, I am developing UD3.3A for full digital signal input phase shifting. At present, I am completing the work of writing the hardware logic of the phase shifting part of the alternating hard switch bridge arm. Hope to share with you more! Thank you!
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Michelle_ March 17, 2024, 04:17:51 AM
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Where's all this voltage coming from?
[Spark Gap Tesla Coils (SGTC)]
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Terry March 17, 2024, 01:29:32 AM
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Re: DRSSTC Questions
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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flyingperson23 March 17, 2024, 12:33:06 AM
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