Author Topic: PLL SSTC oscilloscope measurements  (Read 6726 times)

Offline Rapy2

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PLL SSTC oscilloscope measurements
« on: December 13, 2020, 01:17:15 PM »
Hello guys,
I am almost beginner.
I built a medium size SSTC, PLL controlled with 4046. I´m attaching a schematic. Today I tried to set the phase close to zero current switching, but I have a problem. When the oscilloscope shows the phase setting close to ZCS, my IGBTs get really hot. When I tried to set it so that the transistors warmed up as little as possible and then I measured on an oscilloscope I got a weird result. On the oscilloscope, it looks like if it really was like that, it would mean an immediate explosion, it looks like its switching on the peaks. So I wonder where the mistake is. I use very basic oscilloscope, so I think that this is the problem. I am measuring the current with suitable torroid and about 30 turns and 4,7 Ohm resistor. Is it possible that the oscilloscope is slow and does not measure it correctly? Thank you very much for your help.

Offline davekni

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Re: PLL SSTC oscilloscope measurements
« Reply #1 on: December 13, 2020, 07:03:21 PM »
SSTC circuits do not have any primary resonant capacitor.  The primary switches at maximum current.  ZCS is for DRSSTC.  (Edit:  As Uspring points out later in this thread, ZCS is possible with SSTC if coupling is high enough and secondary Q high enough.)

Most SSTC designs I've seen use FETs.  Fast IGBTs can work for SSTCs in spite of the high-current switching, especially if the enable duty cycle is low.
« Last Edit: December 29, 2020, 06:04:50 AM by davekni »
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Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #2 on: December 13, 2020, 08:44:42 PM »
SSTC circuits do not have any primary resonant capacitor.  The primary switches at maximum current.  ZCS is for DRSSTC.

Most SSTC designs I've seen use FETs.  Fast IGBTs can work for SSTCs in spite of the high-current switching, especially if the enable duty cycle is low.

Ok, thank you very much. I am such an idiot. I didn´t know that. So does it make sense to adjust the PLL with a potentiometer? Or is it enough to set the range in which the resonant frequency of the secondary coil is located?

Offline Mads Barnkob

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Re: PLL SSTC oscilloscope measurements
« Reply #3 on: December 13, 2020, 08:54:30 PM »
SSTC circuits do not have any primary resonant capacitor.  The primary switches at maximum current.  ZCS is for DRSSTC.

Most SSTC designs I've seen use FETs.  Fast IGBTs can work for SSTCs in spite of the high-current switching, especially if the enable duty cycle is low.

Ok, thank you very much. I am such an idiot. I didn´t know that. So does it make sense to adjust the PLL with a potentiometer? Or is it enough to set the range in which the resonant frequency of the secondary coil is located?

You need some kind of resonant frequency (from the secondary circuit) feedback to the PLL, as sparks present a RC load to the secondary circuit. The spark loading will pull the resonant frequency down, the longer the sparks get. This changes for almost every single spark, so without feedback you will not be able to grow long sparks.
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Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #4 on: December 13, 2020, 09:18:47 PM »
SSTC circuits do not have any primary resonant capacitor.  The primary switches at maximum current.  ZCS is for DRSSTC.

Most SSTC designs I've seen use FETs.  Fast IGBTs can work for SSTCs in spite of the high-current switching, especially if the enable duty cycle is low.

Ok, thank you very much. I am such an idiot. I didn´t know that. So does it make sense to adjust the PLL with a potentiometer? Or is it enough to set the range in which the resonant frequency of the secondary coil is located?

You need some kind of resonant frequency (from the secondary circuit) feedback to the PLL, as sparks present a RC load to the secondary circuit. The spark loading will pull the resonant frequency down, the longer the sparks get. This changes for almost every single spark, so without feedback you will not be able to grow long sparks.

Yeah, I know this, but thank you. I have a feedback. My coil is working quite well. Today i get 80cm sparks from it, but I am still little bit confused about the transistor switching, almost every attempt leads to transistors explosion after 20 seconds. I don´t know where the problem is. I use 4 driving chips ucc37322/1 and suitable ferrite core, the output looks pretty nice. My full bridge is in my opinion also ok. The traces are as short as possible, I use freewheling diodes, snubber capacitors 3x mkp10 400V 4,7u, I have gate resistor and zeners to protect gates, so the only thing that occurs to me is just switching the transistors. I saw some circuits with PLL and they described setting the switching of the transistors close to zero current.But I am beginner and don´t know much about this.

Offline davekni

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Re: PLL SSTC oscilloscope measurements
« Reply #5 on: December 13, 2020, 09:46:50 PM »
"almost every attempt leads to transistors explosion after 20 seconds.'

Do you have an interrupter to pulse enable pins of the driver chips (or gates before the driver chips)?  20 seconds of continuous 240kHz hard switching may be more than the IGBTs can handle.

If you would like more detailed help, please post more complete schematics (including IGBT part number) and images of the circuitry and wiring.

That scope should be fine.  Issues are more likely in how a scope is used.  Do you have an isolated Vbus supply, or are you floating the scope ground, or do you have a differential probe?
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Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #6 on: December 13, 2020, 10:38:25 PM »
"almost every attempt leads to transistors explosion after 20 seconds.'

Do you have an interrupter to pulse enable pins of the driver chips (or gates before the driver chips)?  20 seconds of continuous 240kHz hard switching may be more than the IGBTs can handle.

If you would like more detailed help, please post more complete schematics (including IGBT part number) and images of the circuitry and wiring.

That scope should be fine.  Issues are more likely in how a scope is used.  Do you have an isolated Vbus supply, or are you floating the scope ground, or do you have a differential probe?
Right now, I am not using an interrupter, I am trying to run it continuous, but it is probably not the right way. I just saw some videos where they were running it continuously on full power for about 5 minutes, so I thought my coil should do this too.

Yes, thank you, I only build the coil on weekends, so next weekend I will add a diagram and wiring. I use IGBT FGA60N65SMD.

My Vbus is isolated, because I use variac, so it is floating and scope is also floating, I use another transformer for floating the scope. I don´t have a differential probe.

Offline davekni

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Re: PLL SSTC oscilloscope measurements
« Reply #7 on: December 13, 2020, 11:19:50 PM »
First, variacs DO NOT isolate.  (It would theoretically be possible to make an isolation transformer and variac on the same core.  Has anyone seen such an item?)  Your scope is electrically hot.  Take great care to not touch your scope and any ground path (ie. concrete floor etc.).

When floating the scope ground, besides taking great care for safety, I recommend "grounding" the scope probe to Vbus-, not to one of the H-Bridge outputs.  The scope "ground" adds parasitic impedance to the node which can sometimes alter circuit operation or make measurements less accurate.  Ground to VBus- and probe one H-Bridge output at a time (or both using two probes).

The videos that look continuous are likely interrupted, perhaps at frequencies used to play musical notes.  Such pulsed operation generally produces longer arcs than does true continuous operation.  The pulse repetition frequency is faster than video frame rates, so the result looks continuous.  It is possible to run truly-continuous using FETs sized and heat-sunk for that situation.  That's the way my 3kW SSTC runs.  Arcs are short (~40cm max) and thick.

At 60A (roughly what I see on your scope trace), FGA60N65SMD lists 0.78mJ turn-offl switching energy.  0.78mJ * 240kHz = 187W for switching.  Conduction losses add a bit more, perhaps another 40W, for 227W total per device.  If you have good thermal compound and cooling for ~900W total (for all four IGBTs), continuous operation may be possible with these IGBTs.
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Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #8 on: December 13, 2020, 11:24:22 PM »
First, variacs DO NOT isolate.  (It would theoretically be possible to make an isolation transformer and variac on the same core.  Has anyone seen such an item?)  Your scope is electrically hot.  Take great care to not touch your scope and any ground path (ie. concrete floor etc.).

When floating the scope ground, besides taking great care for safety, I recommend "grounding" the scope probe to Vbus-, not to one of the H-Bridge outputs.  The scope "ground" adds parasitic impedance to the node which can sometimes alter circuit operation or make measurements less accurate.  Ground to VBus- and probe one H-Bridge output at a time (or both using two probes).

The videos that look continuous are likely interrupted, perhaps at frequencies used to play musical notes.  Such pulsed operation generally produces longer arcs than does true continuous operation.  The pulse repetition frequency is faster than video frame rates, so the result looks continuous.  It is possible to run truly-continuous using FETs sized and heat-sunk for that situation.  That's the way my 3kW SSTC runs.  Arcs are short (~40cm max) and thick.

At 60A (roughly what I see on your scope trace), FGA60N65SMD lists 0.78mJ turn-offl switching energy.  0.78mJ * 240kHz = 187W for switching.  Conduction losses add a bit more, perhaps another 40W, for 227W total per device.  If you have good thermal compound and cooling for ~900W total (for all four IGBTs), continuous operation may be possible with these IGBTs.

Thank you very much. On the weekend I will add more info about my setup.

Offline Mads Barnkob

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Re: PLL SSTC oscilloscope measurements
« Reply #9 on: December 13, 2020, 11:35:59 PM »
First, variacs DO NOT isolate.  (It would theoretically be possible to make an isolation transformer and variac on the same core.  Has anyone seen such an item?)

It is actually just called a "variable transformer" as a transformer is isolated contradictory to the variac "autotransformer".

I did two videos about it and posted the schematics for the electronic fuse here: https://highvoltageforum.net/index.php?topic=1271.msg9368#msg9368
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Offline Uspring

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Re: PLL SSTC oscilloscope measurements
« Reply #10 on: December 14, 2020, 06:30:26 PM »
It's possible to have ZCS with SSTCs, provided coupling and secondary Q are large enough. A PLL SSTC is a nice experimental setup to experiment with this. Start with a frequency lower than secondary resonance and increase f. Primary current should drop as you would expect from an inductive load. Near the secondary fres, the current should increase and the phase between primary current and voltage should drop, perhaps down to 0. As said, that depends on coupling and secondary Q.

Offline davekni

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Re: PLL SSTC oscilloscope measurements
« Reply #11 on: December 14, 2020, 06:52:04 PM »
Good point about high coupling and secondary Q allowing ZCS.  With 80cm arcs, is it practical for Q to remain high enough?
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Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #12 on: December 15, 2020, 12:28:27 PM »
It's possible to have ZCS with SSTCs, provided coupling and secondary Q are large enough. A PLL SSTC is a nice experimental setup to experiment with this. Start with a frequency lower than secondary resonance and increase f. Primary current should drop as you would expect from an inductive load. Near the secondary fres, the current should increase and the phase between primary current and voltage should drop, perhaps down to 0. As said, that depends on coupling and secondary Q.

Ohh, thank you very much. I am from Czech Republic and one guy from Slovakia made very simillar project and I was inspired from him. He set up on his SSTC ZCS. Here is his website, hopefully the google translation to english will be good enough. https://www.vn-experimenty.eu/teslov-transformator/sstc/sstc-5.html And it let me think, that I can set ZCS...

Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #13 on: December 15, 2020, 12:50:01 PM »
Hello guys,
I am almost beginner.
I built a medium size SSTC, PLL controlled with 4046. I´m attaching a schematic. Today I tried to set the phase close to zero current switching, but I have a problem. When the oscilloscope shows the phase setting close to ZCS, my IGBTs get really hot. When I tried to set it so that the transistors warmed up as little as possible and then I measured on an oscilloscope I got a weird result. On the oscilloscope, it looks like if it really was like that, it would mean an immediate explosion, it looks like its switching on the peaks. So I wonder where the mistake is. I use very basic oscilloscope, so I think that this is the problem. I am measuring the current with suitable torroid and about 30 turns and 4,7 Ohm resistor. Is it possible that the oscilloscope is slow and does not measure it correctly? Thank you very much for your help.

As I promised, I'm attaching photos of my SSTC. Its PLL, I´m attaching my schematic too. The excitation of the GDT is provided by 4x Ucc37322 / 1, always 2 in parallel. I´m powering it from variac, maximum Vbus is 390V. I usually run it just with one diode rectification, because my 16A breaker can not stand full bridge rectifitaion. Secondary coil is 40cm high, 110mm diameter, wind with 0.35mm wire and it runs about 240kHz. Primary is 10 turns, 125mm diameter, 2.5mm wire and with 1cm spacing between turns. The problem is as I described. I tried to set ZCS like the guy to whose site I sent the link in the last message. But there was a problem and it absolutely didn´t work. It always blew up my transistors at full power after 20 seconds. I am now thinking about removing PLL, because it doesn´t work much great with interrupter and add interrupter. Please look at my photos if there is something wrong on my layout. Thank you very much.

Offline Uspring

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Re: PLL SSTC oscilloscope measurements
« Reply #14 on: December 15, 2020, 03:18:41 PM »
davekni wrote:
Quote
With 80cm arcs, is it practical for Q to remain high enough?

Q needs to be about 1/k^2 or more. For an 80cm arc, secondary impedance should be lower than the typical 50k, maybe 15 or 20k. That depends on the value of k.
In order to get ZCS, the current in the secondary needs to be large enough to effectively cancel the primary inductance. That requires large secondary currents, which is the reason for the high Q needed and a large coupling to make the primary feel the secondary current. This situation also implies, that ZCS won't happen immediately after start of the burst, since secondary current has to build up. So this option is more one for CW or QCW coils.

@Rapy2: Thank you for the reference. I've actually never seen a working ZCS SSTC before. My speculation on this was on theoretical grounds.
The cancellation of the primary inductance is usually very incomplete, due to either Q or coupling not being large enough. Often there is just a dip in primary impedance around the secondary resonance frequency. In your case, the dip in inductance seems to be large enough to cause current to rise enough for your transistors to explode. I think it should be possible run your coil with the PLL, so that current levels won't be too high. That's then without ZCS. Do you have data on coupling and secondary inductance?


Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #15 on: December 15, 2020, 03:36:48 PM »

@Rapy2: Thank you for the reference. I've actually never seen a working ZCS SSTC before. My speculation on this was on theoretical grounds.
The cancellation of the primary inductance is usually very incomplete, due to either Q or coupling not being large enough. Often there is just a dip in primary impedance around the secondary resonance frequency. In your case, the dip in inductance seems to be large enough to cause current to rise enough for your transistors to explode. I think it should be possible run your coil with the PLL, so that current levels won't be too high. That's then without ZCS. Do you have data on coupling and secondary inductance?
[/quote]

Thank you, but I don´t really know much about this. A know some parameters of my coil, but I didn´t calculate it. I just tried 2 or 3 primary coils with different diameter and took the primary which gave me the best results.

Sadly I don´t know the coupling or how to calculate it, but from calculations and measuring, the secondary coil inductance is 37,6 uH.
I

Offline Uspring

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Re: PLL SSTC oscilloscope measurements
« Reply #16 on: December 15, 2020, 04:18:44 PM »

Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #17 on: December 15, 2020, 04:36:44 PM »
Have you tried JavaTC?
http://www.classictesla.com/java/javatc/javatc.html

Yeah, but there was a problem. I don´t know how to enter the data about my primary coil. Secondary coil and topload were fine. I have helical coil on 125mm diameter, 10 turns, 2.5mm wire and 10mm spacing between turns. In Radius 1 I enter 12.5cm, in Radius 2 also 12.5 cm, in Height 1 I enter 3 cm, because my primary starts 3cm higher than secondary coil and and in Height 2 I set 3cm+coil height which is 12.5cm=15.5cm, but I don´t absolutely know what I should enter in Ribbon Height and Ribbon Thickness.

Offline Uspring

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Re: PLL SSTC oscilloscope measurements
« Reply #18 on: December 15, 2020, 05:39:54 PM »
You don't need to enter anything for ribbon or lead. Be sure to get the radius-diameter distinction right.

Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #19 on: December 15, 2020, 09:27:20 PM »
You don't need to enter anything for ribbon or lead. Be sure to get the radius-diameter distinction right.

Yeah, you are right. My english is not so good and I thought that radius and diameter are the same. Right now its working properly. Thank you very much :)

Offline davekni

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Re: PLL SSTC oscilloscope measurements
« Reply #20 on: December 15, 2020, 10:07:15 PM »
Thank you for sharing pictures, and for the link to the design the SSTC-III design that inspired you!  That SSTC-III design looks to have high coupling.  Still surprising to me that ZCS operation is possible with large arcs.  I noticed one detail in the SSTC-III design that I wouldn't recommend, although it is obviously working:

Notice that GDT primary leads pass through different slots in the steel case.  That is adding parasitic inductance.  Ideally the GDT wires remain paired (ie. twisted) for their entire length.

Do you have specifications for your GDT core?  That yellow color reminds me of typical powder-iron cores.  Parasitic inductance will be reduced if you use fewer turns on a good ferrite core, such as the four-turn GDT in the SSTC-III example.  It is even better to wind the GDT with four twisted pairs.  One wire of each pair is for secondaries.  The other four wires, one from each pair, are in parallel for the primary.

Another nice feature of the referenced SSTC-III design is that the H-Bridge heat-sink forms a ground-plane immediately under the power ECB traces.  That reduces parasitic inductance.  You could get some reduction by adding copper tape (or aluminum sheet or etc.) to the bottom side of your power ECB, ideally extending to the heat-sinks.  Even better is to implement the H-Bridge power wiring as copper planes as in this example layout I made:
https://highvoltageforum.net/index.php?topic=1324.msg9886#msg9886
David Knierim

Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #21 on: December 16, 2020, 12:12:52 AM »
Thank you for sharing pictures, and for the link to the design the SSTC-III design that inspired you!  That SSTC-III design looks to have high coupling.  Still surprising to me that ZCS operation is possible with large arcs.  I noticed one detail in the SSTC-III design that I wouldn't recommend, although it is obviously working:

Notice that GDT primary leads pass through different slots in the steel case.  That is adding parasitic inductance.  Ideally the GDT wires remain paired (ie. twisted) for their entire length.

Do you have specifications for your GDT core?  That yellow color reminds me of typical powder-iron cores.  Parasitic inductance will be reduced if you use fewer turns on a good ferrite core, such as the four-turn GDT in the SSTC-III example.  It is even better to wind the GDT with four twisted pairs.  One wire of each pair is for secondaries.  The other four wires, one from each pair, are in parallel for the primary.

Another nice feature of the referenced SSTC-III design is that the H-Bridge heat-sink forms a ground-plane immediately under the power ECB traces.  That reduces parasitic inductance.  You could get some reduction by adding copper tape (or aluminum sheet or etc.) to the bottom side of your power ECB, ideally extending to the heat-sinks.  Even better is to implement the H-Bridge power wiring as copper planes as in this example layout I made:
https://highvoltageforum.net/index.php?topic=1324.msg9886#msg9886

My GDT wires are twisted for their entire lenght. But that is interesting, I didn´t notice that and I have read the site more than 10 times.

Yeah, I have specifications. It is this core: https://www.tme.eu/cz/en/details/tx42_26-3e25/ring-ferrites/ferroxcube/tx42-26-13-3e25/
Before I bought this one I used random core from microwave oven input filter and it works very well, but the problem was, that it is small and I can´t use it for full bridge.
Ok, that looks very interesting for me. I will probably rewind my GDT. It is good looking square wave, but it has some spikes and they are much bigger than my previous GDT. This GDT was wound up just by twisting 5 wires together. It has 16 turn on secondaries and 13 turn on primary, so it step up my 13,7V from UCCs to about 18V.
And one quick question. Is it ok to use solid core wire or is it better to use stranded wire? Right now I am using solid core...

Thank you for sending me your article. I will read it as soon as possible. I have some aluminium tape left, so I can use it.

And thank you very much for replying me. I really appreciate it.
« Last Edit: December 16, 2020, 12:34:50 AM by Rapy2 »

Offline davekni

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Re: PLL SSTC oscilloscope measurements
« Reply #22 on: December 16, 2020, 04:15:53 AM »
That GDT core is fine.  Turn ratios other than 1:1 make low leakage inductance difficult.  Most drivers for IGBTs such as UD2.7 (for DRSSTC) us discrete FETs after the driver chips to boost gate voltage to +-24V before the GDT.  There are some driver chips capable of more voltage too.  However, reasonable leakage inductance may be possible with fewer turns, perhaps 4:5.

That core lists cross-sectional area of 95.8mm^2.  Using 0.22T saturation to be conservative (spec. at 100C), that is 95.8mm^2 * 0.22T = 21uVs per turn.  Per your scope plot, a half-cycle on your coil is 2.1us wide.  Thus you can run up to 10V/turn on the GDT before saturation (21uVs/turn / 2.1us = 10V).  So a 4-turn primary and 5-turn secondary would have plenty of margin away from saturation.  You could wind 4 turns with twisted pairs, then add one more turn for each secondary back over the top of the initial four turns to minimize spacing and therefore minimize leakage inductance.  Then parallel the four primary wires.  Best is to keep each of the four primary winding leads twisted with themselves back to the driver, connecting them in parallel at the driver.  That way the lead inductance is cut by a factor of 4.  Solid or stranded makes no difference.
David Knierim

Offline Rapy2

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Re: PLL SSTC oscilloscope measurements
« Reply #23 on: December 16, 2020, 11:08:57 AM »
That GDT core is fine.  Turn ratios other than 1:1 make low leakage inductance difficult.  Most drivers for IGBTs such as UD2.7 (for DRSSTC) us discrete FETs after the driver chips to boost gate voltage to +-24V before the GDT.  There are some driver chips capable of more voltage too.  However, reasonable leakage inductance may be possible with fewer turns, perhaps 4:5.

That core lists cross-sectional area of 95.8mm^2.  Using 0.22T saturation to be conservative (spec. at 100C), that is 95.8mm^2 * 0.22T = 21uVs per turn.  Per your scope plot, a half-cycle on your coil is 2.1us wide.  Thus you can run up to 10V/turn on the GDT before saturation (21uVs/turn / 2.1us = 10V).  So a 4-turn primary and 5-turn secondary would have plenty of margin away from saturation.  You could wind 4 turns with twisted pairs, then add one more turn for each secondary back over the top of the initial four turns to minimize spacing and therefore minimize leakage inductance.  Then parallel the four primary wires.  Best is to keep each of the four primary winding leads twisted with themselves back to the driver, connecting them in parallel at the driver.  That way the lead inductance is cut by a factor of 4.  Solid or stranded makes no difference.

Ok, thank you very much. I will rewind my GDT with just 4:5 wires and hopefully it will decrease voltage spikes.

Offline davekni

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Re: PLL SSTC oscilloscope measurements
« Reply #24 on: December 16, 2020, 07:35:18 PM »
Please check gate waveforms with your scope after rewinding the GDT.  I don't expect the UCC37321/2 chips to have trouble with the roughly +-0.15A magnetization current.  Still good to check before running at high power.  All my experience has been with FETs driving GDTs such as in UD2.7 driver schematics.  I have no personal experience with driver chips connected directly to a GDT.

A bit more explanation:  A 4-turn primary on your GDT core is far below saturation as I posted previously.  The lower turn-count also reduces inductance, which increases current.  The core lists 6.4uH/turn^2, so 16 * 6.4 = 102uH for 4 turns.  That results in about +-0.15A current at your 240kHz frequency.  With FETs driving GDTs, even 1 or 2A isn't problematic.  I think +-0.15A will be fine directly from the driver chips.  Check to make sure.

BTW, when your IGBTs have failed in the past, did the external diodes you have across them also fail?  If so, it is possible that a diode failed first and then the failed (shorted) diode caused IGBTs to fail.
« Last Edit: December 16, 2020, 07:38:38 PM by davekni »
David Knierim

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Re: PLL SSTC oscilloscope measurements
« Reply #25 on: December 16, 2020, 11:27:01 PM »
Please check gate waveforms with your scope after rewinding the GDT.  I don't expect the UCC37321/2 chips to have trouble with the roughly +-0.15A magnetization current.  Still good to check before running at high power.  All my experience has been with FETs driving GDTs such as in UD2.7 driver schematics.  I have no personal experience with driver chips connected directly to a GDT.

A bit more explanation:  A 4-turn primary on your GDT core is far below saturation as I posted previously.  The lower turn-count also reduces inductance, which increases current.  The core lists 6.4uH/turn^2, so 16 * 6.4 = 102uH for 4 turns.  That results in about +-0.15A current at your 240kHz frequency.  With FETs driving GDTs, even 1 or 2A isn't problematic.  I think +-0.15A will be fine directly from the driver chips.  Check to make sure.

BTW, when your IGBTs have failed in the past, did the external diodes you have across them also fail?  If so, it is possible that a diode failed first and then the failed (shorted) diode caused IGBTs to fail.
Thanks for explanation. I will check my gate waveforms on scope. My experience is that this chips works well and I never had a problem. Single UCC chip can output 0.6A current and +-9A peak current. I have 4 chips, every 2 in parallel, so it shouldn´t be a problem. I have read about FETs driving GDT, but this chips work for this medium SSTC well and I want to keep it simple and small.

When my IGBTs have failed in the past, the external diodes didn´t fail. I have MUR1560 across them, but I think, that they are slower than the internal diode in this IGBT (FGA60N65SMD), because when it was running, this external diodes never got even warm, so I think that they were there just for decoration... According to the datasheets, internal diodes have 47ns trr and external 60ns trr, so it looks like I said before.

 

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Re: PLL SSTC oscilloscope measurements
« Reply #26 on: December 16, 2020, 11:51:45 PM »
And back to ZCS. I am attaching a photo of waveforms on my old setup. It is like month ago. It was just a halfbridge and I tried to set up the phase to ZCS. In the picture it is running at full power. Althought the waveforms look good, it is not switching at peaks, the halfbridge always blew up after a few seconds. So I decided to build full bridge, but there is same problem and it is not even possible to set this waveforms, it is switching at peaks.

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Re: PLL SSTC oscilloscope measurements
« Reply #27 on: December 17, 2020, 12:43:34 AM »
The key difference with half-bridge SSTC is the capacitors that that substitute for the other missing half of a full-bridge.  Those capacitors shift phase of the current waveform earlier, making it closer to ZCS.  You can get the same result by adding capacitor(s) in series with the primary coil with full-bridge drive.  If you do that, just be sure capacitance is large enough that primary resonance frequency is well below secondary resonance frequency.  Otherwise you will end up with an unintentional DRSSTC.  With a DRSSTC, primary current limiting circuitry is critical.

A couple people here have added schottky diodes (1N5819 or 1N5818 or ...) from driver chip outputs to driver chip +15V supply.  There's concern that the negative part of the GDT magnetization current (after switching) can cause UCC2732x outputs to go enough above their supply rail to fry driver chips.  It certainly wouldn't do any harm to add those two schottky diodes if you have any similar parts around.  A single diode will suffice for two paralleled driver chips, so only two diodes total are needed.
« Last Edit: December 17, 2020, 02:04:28 AM by davekni »
David Knierim

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Re: PLL SSTC oscilloscope measurements
« Reply #28 on: December 17, 2020, 08:18:08 AM »
The key difference with half-bridge SSTC is the capacitors that that substitute for the other missing half of a full-bridge.  Those capacitors shift phase of the current waveform earlier, making it closer to ZCS.  You can get the same result by adding capacitor(s) in series with the primary coil with full-bridge drive.  If you do that, just be sure capacitance is large enough that primary resonance frequency is well below secondary resonance frequency.  Otherwise you will end up with an unintentional DRSSTC.  With a DRSSTC, primary current limiting circuitry is critical.

A couple people here have added schottky diodes (1N5819 or 1N5818 or ...) from driver chip outputs to driver chip +15V supply.  There's concern that the negative part of the GDT magnetization current (after switching) can cause UCC2732x outputs to go enough above their supply rail to fry driver chips.  It certainly wouldn't do any harm to add those two schottky diodes if you have any similar parts around.  A single diode will suffice for two paralleled driver chips, so only two diodes total are needed.
Yeah, I had this capacitor in series with primary for DC blocking task. I calculated it, so my primary resonance was about 25k, so it was ok and cannot accidentally work as DRSSTC. I will add it here too.

I don't have this diodes here. I will add them. Maybe it will reduce chips heating. Thank you!

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Re: PLL SSTC oscilloscope measurements
« Reply #28 on: December 17, 2020, 08:18:08 AM »

 


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