Silicon Carbide MOSFETs in a small Tesla coil

[tefatronix]

Hello,


I am thinking about building a small SSTC this year using Silicon Carbide FETs from UnitedSIC. This is the model I selected - UF3C065080K4S  (650 volt, 80 mOhm, 43 nC gate charge) and would like to drive them using the UCC21520 gate driver. In my calculations and simulations, the typical leakage of a GDT (few tens to hundred nH) would slow down the gate drive too much. The above mentioned MOSFETs are cascode configured as a SiC JFET driven by a Si MOSFET, so they can be driven like normal MOSFETs. Their specified rise/fall time is 8/20 nsec with 8.5 ohm gate resistance.


The planned specs are two of these FETs in half-bridge configuration at around 1 MHz in mains half-cycle "staccato" or filtered+interrupted mode with primary current around 20 amps RMS (which would give around 14 amps RMS per FET). Considering I am able to get ~30 (25-35 cm) sparks with my IRFP460N full bridge SSTC especially when in staccato mode with some 11-15 A RMS (there's 11 in the article but I changed it since) at 320 volts peak bus voltage, I think that half-bridge I might get sqrt((160*20)/(320*15)) times that spark length, so maybe 25 centimeters with decent reserve? With a really compact driver (aiming for ~8x8x5 cm  for ~10x5 cm secondary).


Another SiC FET, the C3M0280090D (900 volts, 280 mOhm) looks amazing for Class E HF SSTCs. That one might be pushable to upwards of 10 MHz (maybe 13.56 MHz ISM band?) as its damn crazy fast (10/7.5 ns rise/fall with 150 pF gate capacitance  and only 9.5 nC (!!!) gate charge). And isn't too expensive.


Are there any good tested (in SSTC duty) gate drivers for such high frequency applications? The well known TC44x2 or IXDD6xx are available even in a nice 5 lead TO220 package for simple heatsinking. All the more modern, fast gate drivers are either in not-so-easily solderable/heatsinkable packages or crazy expensive (IXRFDxxx).


Or is it plausible to run a driver like TC4422 or the IXDD drivers at 13.56 MHz, given that the loading capacitance is low enough and it's heatsinked decently? The propagation delay is already ~1/2 of the period...


Is there something one should watch out when using SiC FETs, except PCB layout being more critical and asymmetric gate drive for non-cascode types? The non-cascode types have no avalanche ratings, so I suppose those are more susceptible to overvoltage damage...

[T3sl4co1l]

Mind the gate voltage limits; whereas a Si FET might actually die at 30-80V, apparently they make the gate oxide on SiC types very thin and precise, so when they say +20/-6V or whatever, abs. max., they mean it.

Use recommended on/off voltages.

Typically you'd use a higher voltage driver like IXDD609YI and tie source to a small positive bias, thus obtaining say +16/-4V gate drive, for a 20V total supply with 4V bias.

The die is very much smaller, which doesn't affect power dissipation all that much, fortunately -- it's as much thinner as it is smaller -- but this means the thermal time constant before failure is that much tinier.  Design in fault protection, and make sure it acts within a few microseconds.

These go doubly for GaN, which is even more power-dense, and rated for even less gate voltage (typically +6/-0).  GaN is also so damn fast that layout is absolutely critical, even with a multilayer design.  (You probably wouldn't choose GaN for a TC, no, but if you did, it could be the tiniest thing ever...)


In terms of pulsed operation, this means: for long pulses, you'll be limited to operation close to the continuous power dissipation rating, so you will simply need whatever inverter capacity is required for a given output power.  Or for a given pro-rating at short pulse widths, the pulse width will be that much shorter.

On the one hand, a burst of say 100us may not be all that impressive, but on the other, the carrier frequency can well be higher as you note, so you can still potentially be pretty far down the ring-up.  Which means you at least aren't suffering any disadvantage in spark length, if perhaps in girth or intensity.


On a related note, it's too bad there isn't much tech for energy storage.  There are poled (electret) ceramic capacitors for DC link applications (e.g. Vishay Ceralink), but they're still preposterously expensive, AFAIK.  Nice thing is, whereas ceramic caps lose capacitance rapidly with rising voltage, these are biased to maximize capacitance around the nominal operating voltage, say 400V or whatever.  So they store a ton more energy, most of the charge being taken under real bias, 250-500V say, unlike the regular case where C just keeps dropping and dropping as V goes up so the energy storage is rather modest.

Tim

[davekni]

Thank you for the pointer to an interesting SiC FET (UF3C065080K4S)!  It lists +-25V maximum Vgs, which should be plenty to cover overshoot if driven to +-12 or +-15 with a transformer.

Concerning leakage inductance, you should be OK with careful gate-drive transformer design/construction, even with fairly-low gate resistance.  For example, if you use 5.5 ohms external resistance, with the part's internal 4.5 ohms gate resistance, that's 10 ohms total.  The average input capacitance (total gate charge / total gate voltage swing) is about 2.5nF for these parts, for a 25ns time constant with 10 ohms.  A total leakage and wiring inductance of 250nH would be critically-damped (also 10 ohms at 25ns).  250nH should be achievable.  (That's 250nH for one FET.  If using a single transformer, any primary inductance will be equivalent to 4x as much per secondary.)

From my experience with gate-drive transformers feeding fast FETs, the big issue will be inter-winding capacitance.  The very-fast voltage steps seen by the sources of the upper two FETs in the bridge couple a lot of current into the transformer (via winding capacitance), causing glitches in the gate drive signals, leading to high-frequency oscillation at the transitions.  Unfortunately, the solutions to winding capacitance usually increase leakage inductance:  Physical separation of windings and/or electrostatic shielding between windings.  I'm guessing a gate-drive transformer solution is still possible, but would need to experiment to see.  Your planned high-frequency (~1MHz) operation helps, allowing fewer turns on the transformer.

Another option is integrated isolated drivers such as Si8274 (what I use in my 80kHz DRSSTC, with a discrete buffer between its output and each set of 10 IGBT gates).  I haven't looked at 1MHz operation, however.

[T3sl4co1l]

Regarding GDTs, first priority tends to be Zo, then CMRR.  Use several pairs in parallel to get Zo down, for example two pairs twisted together (alternating PSPS), also known as "star quad", gets about half the impedance of two twisted pairs wired in parallel (or ~25 ohms).  Ideally you want to match Zo = R, but every bit closer helps.

Use a relatively large, high-mu core to keep winding length minimal.  Leakage inductance is proportional to winding length.

You can always improve CMRR by introducing common mode chokes.  Same thing, use a high-mu core, minimal winding length.  Add damping if necessary, since you're making an LC circuit with the GDT capacitance and CMC inductance.

And consider using a small signal transformer or optos to couple the signal over, DC-DC converters for remote power, and local gate drivers (with desat protection if possible) for best performance.  This is the easiest way to ensure adequate drive to gates with tight requirements (like +15/-4V or whatever, which, good luck doing that with transformers alone).

Tim

[tefatronix]

Thanks for the responses.

Will definitely keep the smaller thermal capacity (and more sensitive gate non-Si+SiC-cascode SiC MOSEFTs) in mind.

I don't think I'll get too close to the maximum settings in my use case, should be a regular SSTC able to run at fairly high duty cycles (if I eventually get to building it )

The Si8274 driver looks interesting. Similar to the UCC21520 and a bit cheaper.

GaN FETs look interesting, but seem too sensitive to everything - ESD/voltages . Found the LMG5200 module which integrates both the FETs and drivers, even saw it used in some small SSTCs online, but only good up to 80V... still, the speeds are amazing.

Also looked at some TO-247 Cascode GaN FETs by Transphorm such as TP65H050WS, these look great but are quite pricey compared to the SiC MOSFETs or Si/SiC cascodes. Considering these basically are a normal Si FET (on the input) with a GaN JFET and generally look somewhat similar to the cascode SiC FETs I posted, they should be less sensitive to the gate drive (rated +-25V). These look quite usable for Tesla coil duty with careful layout. I don't plan to use them, but the parameters look quite nice.

[Weston]

SiC and GaN semiconductors are pretty cool and have been a bit of a game changer in some areas of power electronics. Most of my PhD research revolves around wide bandgap semiconductors in one way or another. Until you start reaching high frequencies (100's of KHz - MHz), the biggest advantage of SiC and GaN parts is reduced / no body diode recovery charge, which allows you to hard switch with a lot lower loss. At higher frequencies the lower capacitance is an advantage for resonant switching schemes, like class E.

Driving SiC devices at high frequency is a bit tricky because of the high voltage swing they require compared to GaN. Gate drive ICs that can supply these voltages dissipate a fair amount of power. There are some interesting resonant gate drive schemes you can try though to reduce power and user lower voltage gate drive ICs: https://superlab.stanford.edu/poster/ECCE2019_paper_Zikang . You can buy GaN gate drivers that go to 40MHz+ with few issues. I built a little push pull class E GaN coil that runs at 6.78MHz a few years ago and it worked pretty well, but heatsinking was a bit of a pain because GaN devices have small packages: https://www.flickr.com/photos/63341195@N08/37327569382/in/album-72157650804366725/

Cascode devices are convenient because you drive a Si gate and can use a normal gate driver, but they are somewhat slower and higher loss than a non cascode device, especially for GaN, and can have problems with oscillation / stability. Your best option would be to use an isolated gate driver + isolated power supplies. I am using UCC5390SC and R15P21503D in the SiC based QCW coil I am currently working on. That could push 1MHz without issue. With isolated gate drive instead of a GDT you can also do some more interesting control things.

[RosBaig]

Hi...I've built a few coils of diverse sizes extending from little frameworks to a few or maybe expansive ones. Expansive coils are regularly amazing when running at tall control, but they posture a few calculated challenges in terms of building them, putting away them, running them and setting them up (and not to specify, they're lovely costly!). Since of this this, I've been working on building littler coils, and it has been very a parcel of fun! Turns out, building physically little coils has its possess set of challenges related with them as well.

https://www.7pcb.com/

[nick]

Hi,

I found this thread after seeing a video about SiC MOSFETs and wondering whether they've been used in a SSTC.

How did it go, OP? Did you manage to create one?

Thanks