Benjamin's DRSSTC 2 in progress

[Benjamin Lockhart]

Thanks Dave, I'll do that

[thedoc298]

Very nice looking gear, I was wondering on your primary, it looks like your connected to the outer and the inner. How are you moving the tap, as I don't see any.

[Benjamin Lockhart]

You can see the tap point here.


I've mostly finished rebuilding the coil now. Hopefully this aluminum block will be enough heatsinking for the rectifiers.








Making things fit.


I put a few extra CTs on the bridge outputs to check current sharing and it appears to be identical on 2 separate bridge outputs!

[Benjamin Lockhart]

Hi all, Here's an update on this project.

First light was making 7 foot sparks at 100us and 240V in with minimal tuning, but a primary strike and flashover to the bottom secondary turn seems to have killed the FPGA in the UD+.

I suspect that equidrive was a bad idea and the high voltage on the inner primary turn could have caused a spike on the ground line during flashover, but I really don't know.

I've since replaced the driver with a spare for now, reconfigured the MMC for higher primary impedance (now 0.296uF instead of 0.67uF) and no equidrive.
I simply paralleled the bridge outputs.
I also raised the secondary an inch to lower coupling to about .142


Here's the new test run at only half input voltage 340V bus, and 500us on time. It has hit 7 feet now at only 120V in and trips the 20A breaker quickly. There is 240V 50A available  for full power.
I'd like to build a better toroid with less unwanted breakouts before trying 240V in.

[flyingperson23]

.296uF seems small enough to really limit your current. That also probably makes it sound fuzzier at low bus voltages. I think it'll sound a lot better at full power, especially if you turn up the duty cycle.

[Benjamin Lockhart]

Yes it is, I might change it to 0.44uF with a larger toroid. The initial current ramp up gets to 750A and the steady state current when I turn it up to 2ms is about 500A. This is just at 340V bus.