IGBTs keep dying (un-solved again)

[TMaxElectronics]

EDIT:Some more issues are occuring again :/

Hey guys,
I just built my first DRSSTC with my own design but am doing something wrong because the IGBTs keep blowing up.
I am using IXXN110N65C4H1 transistors in a full bridge driven by two L6494 GDT-less drivers.

For testing I limited the supply voltage to 110V DC, was running without a resonant secondary (i just use a too small coil to limit the voltage, as i had to test on my workbench), had OCD set to ~200A and had a signal at 100uS on time on the interrupter.

All is fine until (after running fine for around 30mins) on side of the bridge releases the magic smoke. And i have absolutely no idea what could cause that anymore. I re-calculated the dead time and have a safty factor of > 3 (min. should be ~150ns and i have 500ns), the current is well within the pulse current rating of 470A, the IGBTs stay at around 50-60° terminal temperature (so the relatively high on time should be fine?) and there was no arc over from the HV side.
Looking around on the forum here I found something about IGBTs potentially latching up when the datasheet ratings are exceeded, but i think should be within them (200A<470A?).

I think my driver should be fine too, as i tested it for a while using an induction cooker PCB as the primary bridge and it ran fine, making some really nice arcs.

Attached are pictures and the schematic and board files for both the driver and the bridge, but I did modify the bridge driver to have additional bootstrap diodes (the chip has one built in) and am now using the kelvin emitter on QE2. Didn't get around to changing the schematic yet.

Is there something that I am overlooking here or did i just make a poor component choice?

Oh and I am designed everything from scratch because I like a challenge and want to learn by making mistakes and then fixing them.

[Netzpfuscher]

You have no foil capacitor on the bridge. It can be possible that th IGBTs died from overvoltage. You should add a snubber capacitor direct on the PCB.
Have you measured the CE voltage over the IGBTs during switching? Perhaps they desaturate on high pulse current.

[TMaxElectronics]

thanks i will try that once new transistors arrive.
Any opinion on using the capacitors from the induction cooker as a snubber for testing?

And should i perhaps try different IGBTs and, if so, any recommendations? Target switching frequency would be around 80-90kHz according to javaTC
I chose the ones i currently use for the fairly high switching speeds
I remember finding a list with common ones somewhere but don't seem to find it anymore

[ritaismyconscience]

Try reducing the length of the wire from the capacitor to the IGBT.

More wire means more inductance which can cause voltage spikes.

Adding snubber capacitors would help, also consider adding TVS diodes

[davekni]

Adding local film capacitors to the H-Bridge bus supply is the most important fix.  Short paired wires from the bulk caps will help too.  Yes, the 2-10uF induction cooktop capacitors would be good, as many as fit.  Low-inductance connections for these film capacitors is critical. 

Even with those fixes, it's difficult to have control circuitry sharing the same ECB as power connections, especially with only two ECB layers (which I'm presuming here).  It's best to have one ECB for the power connections (IGBT source/drain connections and local VBus film capacitors).  One layer is for VBus+- with a row of film capacitors joining the two halves.  The other layer is for the H-Bridge outputs, at right angles to the VBus rectangles on the first layer.  The control board could live just above the film capacitors, with short twisted-pair wires to each gate/source pair.

[ritaismyconscience]

Another big problem I see is that your MMC seems to be only rated for 1000V. The voltage rating is way too low, as the voltage across the capacitor is at least an order of magnitude bigger than the voltage at the bus due to resonant rise.

You'll probably have to fix that too at some point (with a non resonant coil the voltage probably is under the rating though)

[TMaxElectronics]

Ok thanks for the help guys
I was half expecting to be torn apart for the stupid mistakes i made (as happened to me on other forums before).

So tomorrow I will re-design the driver board, split the circuitry into two PCBs (one pcb will have the power connections the other the gate drivers).
I think I can make some brass standoffs that would allow me to put the reservoir capacitor bank i have now (see the picture in the top post) upside down, almost directly onto the PCB with enough space to fit the film capacitors underneath it.

Do you think i can also use 5mm standoffs to mount the board with the film capacitors and power connections onto the IGBTs, leaving enough space to put the PCB with the gate drivers underneath it (so the stack would be IGBTs -> gate drive PCB -> Power pcb)? I would like to avoid as much loose wiring as possible.

And the MMC already had a bad time while I was testing it (i could actually see arcs in the caps) so I have ordered 15 new ones so i can use 5 parallel x 3 series.

I also remember my Professor talking about (and i think also read a post about) using a snubber network directly across the IGBTs, as shown on page 9 of this document
but have not seen this used in any of the schematics for DRSSTC bridges that I looked at. Would this be worth including?

[davekni]

Snubbing directly across IGBT C-E terminals is generally not used for DRSSTC.  Such snubbing is more needed with hard switching.  DRSSTC control should be switching IGBTs when current is close to zero, ideally just before current reaches zero.  Make sure your controller is switching the gates just before zero-current points.  I don't spot any phase compensation in your circuit.  Did I miss finding that?  Or are you aiming for almost 180 degrees phase lag instead of lead?  Lag can work;  I've done that before.  Since there's already delay in all the circuit stages, added delay can be easier then adding phase lead.  However, lag is usually more sensitive to frequency shifts as arcs increase top-load capacitance.

Figure 5-5 on that Fuji app-note shows the VBus wiring inductance as "Ls".  The key is reducing Ls by placing film capacitors on the power ECB, with VBus+- routed by power plane shapes, not just traces.

Yes, 5mm copper or brass standoffs should be OK.  Not steel - skin depth is low for steel because it's ferromagnetic.  Slices of copper tubing works.  However, scope probing is difficult with hidden control electronics.

For IGBTs, make sure one emitter terminal is used for the power connection, and the other is used for gate-drive return.  This is called "Kelvin connection".

[TMaxElectronics]

I don't spot any phase compensation in your circuit.  Did I miss finding that?

Ah yes, you found another rookie mistake i made 
I kind of just expected the delay to be small enough to ignore when making the circuit, but i just ran the numbers and they speak for themself: at 100kHz with the low pass filter with R4 & C1 in the circuit the overall phase shift of the circuit is 30°, so with a peak current of 250A the IGBTs would switch at 125A.... (even without C1 the lag would be 8°, a lot more than i had expected).
Guess i should have just used my brain from the start and calculated it instead of guessing 

So could i just switch around R4 and C1 to make a high pass filter (als ochange R4 to something like 4.7kOhm or even better a trimmer) to create a phase lead of 8°? And if so, wouldn't a slight change in input frequency during tuning cause a large change in phase lead from the filter?

[davekni]

The most common design on this forum, on any of the UD2.X drivers, is a variable inductor in series with the CT load resistor, R1 in your schematic.  That makes closer to stable phase-lead time, with phase lead increases in degrees as frequency increases.  Another option would be a capacitor across your R2.  That isn't quite as close to constant-time unless R3 is small compared to R2, but still better than a series capacitor (better than trading C1 and R4).

The down-side of any such phase-lead circuit is emphasis of high-frequency noise.  Doesn't seem to be a real problem.  However, I wanted less high-frequency peaking, so designed a RLC filter that has the correct negative-delay over my intended frequency range (50-80kHz), but rolls of at higher frequencies.  Designed by playing with AC plots with LTSpice simulation.  It's in the lower-left of the second schematic page of my DRSSTC post to this forum:
https://highvoltageforum.net/index.php?topic=798.msg5332#msg5332

BTW, did you built your current transformer?  It's difficult to find commercial ones intended for 100kHz.  Low-frequency CTs can result in grossly-inaccurate current values and additional phase lag.

It's best for low-noise and low-loss IGBT switching to switch slightly before zero-current.  That way the remaining current can make the voltage transition gently (and with nominally no power loss) during the dead-time while neither IGBT is conducting.  Then the opposite IGBT turns on before the current switches polarity.  The turn-on is at zero voltage and almost zero current.  With switching after zero-crossing, the IGBT turning-off has it's diode conducting.  The IGBT turning on must conduct the reverse-recovery charge of that diode while at full bus voltage, which can cause large VBus current spikes, followed by a large VBus voltage spike as that current ends.

[TMaxElectronics]

Ok so I played around with LTSpice a bit and got to (what i think) would be a reasonable input network.



The dotted line is the required phase shift, assuming a driver delay of 250ns, and the green line is the phase shift between CT output and comparator input. The delta is always under +1.5°, even up at 150 kHz, and is always positive (so pre-switching is guaranteed).
Sorry for the poor color choice, i hope it is still readable enough.

This would be the new circuit:


Would this be good enough or should I still add the inductor to the input?
And can somebody maybe explain why the inductor causes phase lead? I thought inductors always caused lag.

BTW, did you built your current transformer?

No i didn't. I ordered a 40Hz-200kHz current sense transformer from digi-key, only to realise after it arrived that the listing was wrong at it was only rated for up to 1kHz. But since it still worked i decided to use it anyway, expecting there only to be a lower current output, and no lag.
But i guess the inductance would cause some. So i will wind my own

Just as a side note: i just realised how much i learned at uni in the last two semesters. When I designed the driver I was just through my first semester and thinking about the design choices again now, they honestly seem like stupid gut feel choices, instead of actual engineering.

[davekni]

That circuit looks good.  The only caveat to mention is that the phase lead will change (increase) a bit at high current when the clamp diodes conduct.  A time-domain simulation will show if that's enough to be of concern.

For ideal inductors, current lags voltage by 90 degrees.  That means that voltage leads current by 90 degrees.  When driven by current and sensed as voltage, inductors generate phase lead.

Feel free to post layouts, especially of your new power ECB, before ordering.  That way you can include advice before spending money.  That's similar to standard industry practice of design reviews.

One more layout option is to use two heat sinks with two IGBTs each.  Then you can leave a gap between heat sinks for film capacitors to mount on the under side of the power ECB.  This allows the power ECB to be below the gate-drive ECB for better gate scoping access.

[TMaxElectronics]

Ok the new PCBs are done.
I added the phase compensation network to the driver, added 4 snubber caps (each with 4uF rated for 450V) to the bridge, split the bridge pcbs into two as I planned and added a snubber to the triac controlling the capacitor charge relay but did not add any TVS diodes across the IGBTs. I will not use two heatsinks, as i don't want to cut the exsisting one in half, and would like to use the heatsink i already have.

Is the bridge layout acceptable like this? The film capacitor placement is the most reasonable to me but has fairly large loop length; is it too much?
The traces on the power board are on both top and bottom layer (i don't know how to make layers transparent in altium so you have to trust me ) and i kept a spacing of >3mm for all high voltage signals. Seems quite little to me, but that's more than what Saturn PCB toolkit calculated for a voltage of >500V so i guess it will be fine. Just in case I added a routing path in places where clearance is less than 5mm (the PDF somehow doesn't show these).
The snubber caps i took out of the cooker are B32676T4405K000, but the Irms rating worries me slightly as they are only rated for 6A each, but 4x6A = 24A  /10% duty cycle would still mean 240A ripple current while switching, is this a valid calculation or do i need to look for better ones?

I was also wondering about my choice of reservoir capacitors, they are ALS70A332KF350 3.3mF 350V ones with a rated ripple current of 16A @ 10kHz, so again with the above calculation that would be >600A ripple during switching.

Just to be sure: for the interrupter signal i am planning to my midi synth stick (just a usb capable pic uController on a board with an optical transmitter).
So far i have programmed an adjustable signal on-time with duty cycle limitation, is there any other requirement for the signal that i am missing?

EDIT: i just noticed that the signal connector on the IGBT driver board is unaccessible when the power board is on top, so i will change this before ordering

[ritaismyconscience]

If you want to, you could also figure out some way to mount the electrolytic capacitors on top of the board also, which would reduce inductance.

[TMaxElectronics]

you could also figure out some way to mount the electrolytic capacitors on top of the board

That was my plan 
I will just make some brass spacers and nylon insulators to hold the capacitors on the board like this:

[davekni]

Nice mechanical design!  Are you double-majoring in electrical and mechanical engineering?

For the power ECB, think in terms of all copper on both sides as the starting point, removing only the minimum necessary to isolate the different circuit nodes.  Given your nice mechanical layout for the film caps, it would be best if you could rotate the electrical assignment of the IGBTs by 90 degrees, so that the bus voltage connections are on the left and right, and the H-Bridge outputs are on the top and bottom.  That way one layer of the ECB can be VBus+ and VBus-, all copper except for a 2.5mm vertical gap in the center, and gaps around IGBT terminals.  The other layer can similarly be all copper except for a horizontal gap in the center separating the two H-Bridge outputs.  Having just those small gaps in copper limits paths for magnetic fields, so reduces inductance.  Copper from the other layer further blocks magnetic fields from squeezing through the gap on one layer.

I'd further suggest that the power ECB have no holes or pads for the gate and associated emitter terminals.  Just leave off the spacers for those.  This reduces the holes in power planes.  (You might need to make a custom ECB symbol for the IGBT with only two terminals.)  If you stay with all four IGBT terminals, then I suggest rotating the IGBTs so that the power connections are towards the center to shorten the power connections.  Gate drive can better handle the extra lead length.

I noticed one other item after looking a bit more through your schematics, the 15V connection from C6 out to J2 for gate drive.  The power and ground have a common-mode choke L1.  Common-mode chokes are great, but the logic signals need to pass through the same common-mode choke (A-Out and B-Out).  Otherwise any voltage drop across the choke becomes added noise to the logic levels seen at the receiving end.  So, either L1 needs to be removed, or L1 needs to become a four-wire choke including A-Out and B-out.  Also, the interconnect impedance is likely closer to 100 ohms, so I'd suggest changing R32 and R33 to ~68 ohms or whatever achieves ~100 ohms when added to the output impedance of Si8232.  Of course, your wiring may be short enough that impedance matching doesn't matter.

At work, I think we use 2.5mm for 500V spacing.  Should be fine unless you plan to run it on Mt. Everest:)  My DRSSTC power ECB has only 1.5mm gap for 450VDC.

Concerning film capacitor RMS current, you may be a bit over their RMS rating, but you also don't need high reliability for years of continuous operation.  These caps see well less RMS current than the H-Bridge output current, as a significant part of VBus current is DC.  Run some simulations and measure RMS current, including averaging over some bursts.  You'll see that RMS current scales by sqrt(duty-cycle), so 10% duty cycle gains only 3.16x reduction.  With your tight connection to bulk caps, they'll likely share a significant amount of the ripple current, so I still think you'll be OK there.  I think your bulk caps will be fine too.  (In industry you'll more likely be designing for long-term continuous use, so will need to simulate more carefully and design for margin.)

For interruption, the main requirement is reasonable limits on duty cycle and pulse width.  I haven't studied your schematic enough to know for sure, but hopefully it's synchronizing the end of each enable pulse to a current zero-crossing point.  I see the flip-flops, but haven't traced the exact operation.

[TMaxElectronics]

Are you double-majoring in electrical and mechanical engineering?

Thanks! But no I am not My mech-eng skills are hobby level at best i just rendered it with blender to make it look good

rotate the electrical assignment of the IGBTs by 90 degrees

Do you mean like this:

That might make it quite hard to access the bridge output terminals though.

any voltage drop across the choke becomes added noise to the logic levels

I guess i will just delete it then. Im not sure how much it actually does here anyway.
I also don't quite understand the impedance matching idea here. It is needed, as without them the driver inputs died because of excessive ringing on the end of the cable (Vpp > 35V) but i don't understand what exactly to calculate the load impedance from. Is that only coming from driver / cable capacitance or is there something more to it? And if so wouldn't i also need to compensate for complex impedance aswell (my networks prof explained this but I don't remember what he said )

EDIT: The interrupter is synchronised to the zero crossing point. The comparators have a latch input that i use for OCD & Interrupter.

[davekni]

Is the power ECB only 1 layer?  My suggestion was presuming two layers, so the H-Bridge outputs could be on their own layer.  What I was attempting to describe is what you showed except with QE2 swapped with QE3.  Then VBus+ connections are all on the top half and VBus- on the bottom half.  H-Bridge outputs would be on the left and right, connected by half-planes on the other ECB layer.  I was also thinking of using the emitter terminals adjacent the collectors for the power connections, and rotating the individual IGBTs so that C/E pair is towards the center (towards the film capacitors).  This last bit isn't as important.

H-Bridge terminals could be at corners, or the board width could grow a bit for H-Bridge terminals to be centered vertically on the left and right.

The noise you were seeing on driver inputs may be due to that 15V/gnd common-mode choke.  With high-impedance series resistors, they and the wiring and load capacitance behave more like a low-pass filter, so that may be helping.  If the cable is long enough, the R/C exponential waveform will look more like a step-function approximation due to the cable reflections.  Yes, the capacitance of the load does matter.  If the source series resistors exactly match the cable's impedance (cables distributed inductance and capacitance), then the receiving end sees a pure R/C waveform based on receiver capacitance and cable impedance (which is the driving impedance).  The actual cable impedance depends on the wire diameter and spacing.  100 ohms is typical for a signal on ribbon cable with a ground (or other DC signal) on either side.  If the delay down the cable is short compared to the response time of the receiving chip, then these transmission-line effects aren't important.

Since you had noise issues in the past with this connection, I'd suggest removing (bypassing) the existing common-mode choke, then feeding the four-wire cable for a few turns through a ferrite core between the controller and gate-drive ECBs.  The clamp-on EMI filter ferrites work well if the cable is already terminated at both ends, preventing it from being fed through the center of a solid ferrite core.  (In general, ferrite cores around cables can solve both operational issues due to noise and EMI issues.)

[Mads Barnkob]

Very nice design and brave of you to take on the journey of building it all from scratch.

One of the reasons that Steve Ward still have documented all his old drivers on his website ( stevehv.4hv.org ) is that there was timing or race condition issues and the evolving into next driver was added more gate, logic or delays to combat these small errors that made everything suddenly go poof.

UD1.3b ( http://stevehv.4hv.org/new_driver.html ) and UD2.1b ( http://stevehv.4hv.org/leadcomp/ ) are still state of the art drivers in my book. Simple, robust and can be built from salving almost anything in your home
That being said, drivers like 2.3, 2.7 and 2.9 are all very good drivers based in the principles of Steve Ward, but with added functionality and helping circuitry.

I don't spot any phase compensation in your circuit.  Did I miss finding that?

Phase lead compensation is a rather new thing in DRSSTCs. It was just an issue with slow bricks when moving up past CM300 bricks. Even Steve Ward Universal Driver 1.3b will do a good job, phase lead compensation was invented to lower losses to push the bricks even further. So I would not suspect no phase lead for failure in these miniblock IGBTs. I run my DRSSTC1 ( http://kaizerpowerelectronics.dk/tesla-coils/kaizer-drsstc-i/ ) with a UD1.3b on 60N60 miniblocks at 500A and the only time it exploded on me was a "silent" death.

At work, I think we use 2.5mm for 500V spacing.  Should be fine unless you plan to run it on Mt. Everest:)  My DRSSTC power ECB has only 1.5mm gap for 450VDC.

It has been seen many times that people have flash overs on inverter PCBs in DRSSTCs, as we have little to none space constraints, just add plenty of respect distance

Concerning film capacitor RMS current, you may be a bit over their RMS rating, but you also don't need high reliability for years of continuous operation.  These caps see well less RMS current than the H-Bridge output current, as a significant part of VBus current is DC.  Run some simulations and measure RMS current, including averaging over some bursts.  You'll see that RMS current scales by sqrt(duty-cycle), so 10% duty cycle gains only 3.16x reduction.  With your tight connection to bulk caps, they'll likely share a significant amount of the ripple current, so I still think you'll be OK there.  I think your bulk caps will be fine too.  (In industry you'll more likely be designing for long-term continuous use, so will need to simulate more carefully and design for margin.)

I wrote a few simple ways of estimating if your electrolytic capacitors are good enough in my DRSSTC design guide: http://kaizerpowerelectronics.dk/tesla-coils/drsstc-design-guide/dc-bus-capacitor/

Adding to the latest posts as well:
- Use double sided PCB to lower the inductance by having positive and negative DC bus on each their side, as Davekni suggests.
- You had problems with noise on your GDT less driver ICs and they are located just inbetween the IGBTs, all this testing you have done was that making sparks with secondary circuit in place as load or has all testing been on a static load? I would suspect there is issues with those drivers + wires being unshielded as well.

[TMaxElectronics]

What I was attempting to describe is what you showed except with QE2 swapped with QE3.

OK so i finally had some time to work on this a bit more. I think I now understand what you said

I kept a clearance of 3mm on everything, and the connected pads are all poured over (it doesn't show that because of the transparency for some reason)

I wrote a few simple ways of estimating if your electrolytic capacitors are good enough

According to the equations there I should be well within limits of my capacitors

was that making sparks with secondary circuit in place as load or has all testing been on a static load?

I used an old smaller secondary without a top-load (fR > 300kHz), so i would get some sparks (~2cm), but nothing too crazy (I had the base on my table next to my component shelf and wanted to prevent damage).
The noise on the drivers was mainly because of the CMC i had in the power path (it basically didn't change with or without secondary power). But I will add a shielding can to the driver circuit just for good measure (the cables were already shielded).

...the only time it exploded on me was a "silent" death.

Yeah mine weren't really silent at all, one of the pops was louder than a large fire cracker and it literally split all four transistors in half. Guess those 700J all went into that bang