How much propagation delay is too much propagation delay

[Power-Max]

I built a half bridge using some IGBTs, 6 ohm gate resistors, a 2222 and 2907 totem pole current amplifier, the IRS2186 bootstrap gate driver IC, which is driven from a Dead-time-insertion circuit that delays a rising edge by about 200ns and the falling edge by the smallest amount possible, by about 50ns or so).

The problem is when I attempt to close the loop using antenna or secondary base feedback (into anti-parallel high-speed diodes) the output isn't what I expect. The circuit is a good bit away from resonance. And I suspect it may have to do with all these propagation delays adding up: 20ns or so for the IGBTs (turn-on delay), the 170ns of the IRS2186, and the 200ns of dead-time insertion from the circuit I made using some RC circuit, diode, and 74HC86. It all adds up to a maximum worst-case of about 600nS. Or about 20% of the operating frequency (assumed 300kHz, it is actually 320kHz small-signal and drops to 270kHz when approaching the secondary with a ground rod or ground plane or with decent breakout).

If I drive the input with a fixed frequency from a function generator and manually tune it, I can get nice 1 foot long hot continuous wave arcs, and I'm pumping about 880W (measured about 8A) from a 110VDC power supply. I also tried making the circuit have variable dead-time to adjust the power going into the arc but unless I allow it to have an open streamer to air (maximum loading, and maximum damping of secondary) this is not a good technique for audio modulation. I need to be able to pull power back out of the resonant network and return it to the supply, which is done by running out of resonance.

I suspect this may be one of the reasons I can't quite get my PLL tesla coil to work right once I close the loop. I occasionally fry these stupid gate driver ICs or my IGBTs when my PLL locks onto some weird harmonic or outputs a non-symmetrical square wave causing issues for the half bridge

[davekni]

For feedback, your options are:
1) Add enough phase-lead to compensate for the delay.
2) Invert the feedback and add enough phase-lag (additional delay) to get almost another 180 degrees of lag.  I say "almost" because half-bridge switching is most efficient and clean when voltage changes slightly before current zero-crossing.
For your situation, I recommend (2) above.  Adding delay is easier, especially given how much delay you already have.  I've used three stages of series resistor and parallel (to ground) capacitor for this purpose.  Each stage is progressively higher impedance (higher R, lower C) to minimize load on previous stage.

For PLL operation, design the PLL to have a narrow frequency range and fixed 50% duty cycle.  That way it cannot lock to harmonics.

One variation on a narrow-band PLL that I've used:  Start with an open-loop L/C oscillator feeding the bridge.  Adjust it's frequency (variable inductor in my case) to your desired center frequency.  Then add a turn around the inductor as loosely-coupled magnetic feedback.  In my case (SSTC), this turn was secondary current.

[Power-Max]

For feedback, your options are:
1) Add enough phase-lead to compensate for the delay.
2) Invert the feedback and add enough phase-lag (additional delay) to get almost another 180 degrees of lag.  I say "almost" because half-bridge switching is most efficient and clean when voltage changes slightly before current zero-crossing.
For your situation, I recommend (2) above.  Adding delay is easier, especially given how much delay you already have.  I've used three stages of series resistor and parallel (to ground) capacitor for this purpose.  Each stage is progressively higher impedance (higher R, lower C) to minimize load on previous stage.

For PLL operation, design the PLL to have a narrow frequency range and fixed 50% duty cycle.  That way it cannot lock to harmonics.

One variation on a narrow-band PLL that I've used:  Start with an open-loop L/C oscillator feeding the bridge.  Adjust it's frequency (variable inductor in my case) to your desired center frequency.  Then add a turn around the inductor as loosely-coupled magnetic feedback.  In my case (SSTC), this turn was secondary current.

I set my PLL to run at between 180kHz to 320kHz (this range may be a bit on the high side) with a 100pF capacitor and I forgot the values of R1 and R2. I am using the digital memory network, as I want to reduce the phase lag, instead incorporate phase lead. I do this by then adding a BJT as a current source to the VCO capacitor to inject a constant current into the capacitor, creating a permanent offset and a phase lead. The output of phase comparator II is then constantly trying to compensate and switching early. If I go too far the coil output diminishes significantly and gives very hot and short arcs.

I notice that under certain conditions the output from the PLL has a duty cycle that can be quite off from 50%. What causes this? IGBTs also tent to get quite toasty. I need to see if it's ohmic or switching losses, I just wired up a current transformer today but one of the IBGTs gave up before I got a good reading of the RMS voltage of the 0.1 ohm resistor. The current waveform was very distorted and seemed to have an amplitude around 200mV or so. With a 30:1 winding ratio that seems to be about 60A? Running with 2 turns and 110V ~8A input, continuous duty. I guess that is about 240W of power dissipation...  Using a CPU heatsink with a 80mm PC fan running on the 15V supply

[davekni]

My guess for non-50% duty cycle is the phase comparitor output filter bandwidth is too high.  That allows significant VCO-frequency signal to get through to the VCO input.

Most people use FETs for SSTC.  With feedback from secondary (antenna or secondary current), it is difficult to get bridge switching just before primary current zero-crossing.   IGBTs have too high switching loss at 100+kHz to use with hard-switching (switching away from current zero-crossing).

[Power-Max]

My guess for non-50% duty cycle is the phase comparitor output filter bandwidth is too high.  That allows significant VCO-frequency signal to get through to the VCO input.

Most people use FETs for SSTC.  With feedback from secondary (antenna or secondary current), it is difficult to get bridge switching just before primary current zero-crossing. IGBTs have too high switching loss at 100+kHz to use with hard-switching (switching away from current zero-crossing).

Thank you for this input. I thought the SSTC is supposed to operate in the ZVS condition when tuned properly? I opened up LTspice to perform a quick AC simulation (250kHz to 300kHz) to see what's up. I set L1=5uH, L2=25mH (3.5in dia., 10", 950t), Cs=14pf, R1={100k -- 5000Mega} (.step param secondary load), R2=10mOhm (primary series resistance to prevent issue of voltage source across inductor). I found that secondary current feedback can be used to lock on to the secondary frequency, as it is very well behaved, with phase lead < resonance and phase lag following resonance. The median point is where maximum voltage output is achieved. And also as long as the Q factor is high enough and/or the coupling is tight enough, it seems that the phase crosses zero. I don't know if in reality it will be possible to achieve this condition.

The phase of the primary current relative to the excitation voltage is rather strange. It crosses over from inductive region (90 degrees lagging) up into the capacitive region (up to leading as much as 90 degrees), then at the resonant frequency dropping back down into the inductive region. If the coupling is weak or the secondary Q factor is too low (the resistor R1) the result is the phase goes up and down much more gradually, and may not reach fully into the capacitive region. If this is the case, then at the resonance the primary current will be lagging significantly.

[davekni]

I thought the SSTC is supposed to operate in the ZVS condition when tuned properly?

DRSSTCs almost always run in ZCS mode (close to zero-current at the bridge switching point).  SSTCs can run ZCS if coupling and secondary Q are high enough.  Many don't run ZCS.  Using feedback from the secondary (antenna or coil current) makes ZCS difficult to achieve.  ZCS refers to switching close to zero primary current.  DRSSTCs use primary current feedback, making ZCS easier to achieve.

[Power-Max]

I thought the SSTC is supposed to operate in the ZVS condition when tuned properly?

DRSSTCs almost always run in ZCS mode (close to zero-current at the bridge switching point).  SSTCs can run ZCS if coupling and secondary Q are high enough.  Many don't run ZCS.  Using feedback from the secondary (antenna or coil current) makes ZCS difficult to achieve.  ZCS refers to switching close to zero primary current.  DRSSTCs use primary current feedback, making ZCS easier to achieve.

I tried to run the half bridge SSTC with primary feedback in LTspice, but found it almost always ends up running the DC blocking capacitors like resonant capacitors, resonating in the low kHz range, or some parasitic oscillation in the low MHz range, depending on the propagation delay and phasing. This makes sense looking at the phase of the current compared to the excitation voltage. The phase is not that well behaved and not monotonic. The simulation assumes no DC blocking since it is an AC simulation anyway. I could add a series capacitor to see what ends up being the third peak below the anti-resonance and resonance peak of the SSTC.

But for now, I found a potentially serious issue. Besides the fact my bootstrap half bridge w/ dead-time insertion circuit has something like 700ns of total propagation delay, leading to an almost 90 degree phase lag, I used 6.2 ohm gate resistors and BJT totem pole arrangement of common emitters following the IRS2186 IC, I observe massive miller effect when the low side IGBTs is turning on. The gate on the low side IGBT gets pulled up to about 10V when the 110V HVDC supply is applied. Output of half bridge left open circuit. Gate drive is clean with no HVDC supply, following a pretty decent following a pretty decent RC characteristic. Placing an additional 1nf capacitor directly across the gate and emitter of the IGBT has almost no effect. high frequency crap is observed on the output of the BJT. (I am using PN2222 and PN2907, perhaps the bandwidth of these devices just isn't high enough)

I'm thinking that a board redesign may be necessary to place those current amplifier BJTs much closer to the IGBT. or perhaps remove them and use 2 IRS2186 IC's to drive both pairs of IGBTs, this gives the freedom to have them run in either half bridge (2 paralell top and bottom) or full bridge (running out of phase)

[davekni]

Yes, ZCS operation is difficult to obtain in SSTCs.  That is why most are designed with FETs instead of IGBTs, and without attempting to hit zero-current switching.  Also, yes, primary current feedback tends to lock to the lower pole frequency.  QCW coils usually operate at the upper pole frequency, requiring extra circuitry to force operation there.

Do you have diodes across the 6.2 ohm gate resistors?  That is necessary to avoid the miller-capacitance issues you are seeing.  If you already have diodes, then your driver chip is not strong enough for the IGBTs being used, or you need larger gate resistance value to slow turn-on speed.

[Power-Max]

Yes, ZCS operation is difficult to obtain in SSTCs.  That is why most are designed with FETs instead of IGBTs, and without attempting to hit zero-current switching.  Also, yes, primary current feedback tends to lock to the lower pole frequency.  QCW coils usually operate at the upper pole frequency, requiring extra circuitry to force operation there.

Do you have diodes across the 6.2 ohm gate resistors?  That is necessary to avoid the miller-capacitance issues you are seeing.  If you already have diodes, then your driver chip is not strong enough for the IGBTs being used, or you need larger gate resistance value to slow turn-on speed.

I designed the board with the intent of using HY1920W or HY1920P MOSFETs (same part but one is a TO-220 for $0.70 ea, (more like $1.40 now with the silicon shortage, the TO-247 one is $1.40 on average) and it popped at least one of them instantly. Also, strangely, the 15nf||6.2ohm snubber keeps burning up with the MOSFETs but not with the IGBTs, the output waveform is much more square with MOSFETs. My calculations predict 1W of power dissipation RMS, but maybe the peak power is killing it. Also it is only the one side connecting output to VCC, not output to GND. Very strange!

I am using this arrangement of NPN and PNP diodes to drive the IGBTs. I breadboard tested it with 15nf capacitor emulating the gate charge, and it seemed to work fine. I can solder a diode on top of those resistors. (those resistors are massive and they get hot! As does the current amplifier)

If I redesign this board, I'll probably use a local current amplifier near each IGBT rather than doing this single driver driving 2 paralell IGBTs. and probably not the 2222 series BJT's, they seem to be rather slow. Or probably just fix all the problems by going with a GDT like everyone else lol