QCW Version 2.0

[V-Troxi]

Hello everyone,

around two years have passed since I built my first QCW coil

https://highvoltageforum.net/index.php?topic=1788.0

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And even though I could not test it outside yet, am quite happy with the results.
But there are some aspects that are in need of improvement, so it's time for some upgrades!

My highest priority this time is robustness and reliability.
I've already managed to destroy two IGBTs (IXXN110N65C4H1) in the past (improperly set OCD and buggy ramp generator). And I don't really like driving the IGBTs near their 200A limit.
Therefore, I want to increase the current capability of the bridge to get a higher safety margin (and bigger arcs ).
Finding FAST, suitable transistors with more current capability than the IXYS is close to impossible.

So I guess I'll have to build a dual- or even quad-bridge setup.
I have two ideas:
- Build a second bridge with the same IXYS IGBTs (preferred). I'd like to try a laminated bus as well.
- Spend a fortune on 16x SiC cascodes by Qorvo (75A to 120A) and build four full bridges (more work than option 1 ).

I've already asked Jan Martiš about current sharing and he told me that splitting one side of the MMC into two (or four) works fine!

The UD2.7 managed to drive a single full bridge well, but I'm unsure if it can handle two bridges of the IXYS as well.
What do you guys think?

The second major thing I want to improve is the buck driver. My QCW currently uses a simple IXDD630MCI gate driver to control the SKM400 module.
This works well, but I want to improve the OCD that I've added. The current approach uses a CT but I think it's quite inaccurate due to the pulses being DC.
What is the best or standard way to do this? A shunt?

I guess a shunt would require some amplification of the mV voltage drop before it can be fed into the comparator. I'll probably need isolation with an optocoupler as well, due to the IGBT emitter being at high voltages.

I'd love to hear some input on my ideas

Best regards,

V-Troxi

[Anders Mikkelsen]

It seems a bit counterintuitive that you'd need 16 expensive SiC cascodes to replace these four IGBTs, what part numbers were you looking at and how do you gauge their equivalence?

For DC current measurements, the easiest approach is to use a DC-capable magnetic current sensor, like a hall effect or fluxgate based model from for example LEM. Though if you use SiC, it's also an option to use phase shift control and get rid of the buck altogether.

[V-Troxi]

Thanks for the reply!

I think a hall effect or fluxgate current sensor is a good idea. Thanks.
I've found these sensors for a reasonable price. I think they would work and have a decent response time. What do you think?
https://eu.mouser.com/ProductDetail/Tamura/L03S600D15?qs=sGAEpiMZZMsPDRSCoHb1X%252BEtsCkzqCDriAmaHkf3FPo%3D
https://eu.mouser.com/ProductDetail/ICE-Components/ISB-425-A-800?qs=sGAEpiMZZMsPDRSCoHb1X3oMLeD7zgPkVLq3F5K9DrGNmlkP0n8NIQ%3D%3D

Yes, phase shifting would be an option, but that would mean partial hard switching and a would require a new driver, so I'll probably keep my buck converter.

I was thinking of these SiC-FETs: https://www.qorvo.com/products/p/UF3C065030K3S#overview
In order to get a current capability of over 200A I'd need 3 or four bridges.

However I prefer the idea of an IGBT dual bridge as it's cheaper (because I already have 4 IGBTs) and more easy to construct, as the IXYS have screw terminals.
I think the UD2.7 could manage to drive two bridges. For example loneoceans' QCW1.5 featured 8x 50B60 IGBTs which have a higher gate charge than my IXYS. But I guess I'll have to find out.

I would also like to have a display on the front of the coil that shows the last peak value of the primary current (approximately).
I have a crude idea on how I could maybe do it. I was thinking of using a CT and buffering the voltage drop of the burden resistor using a small capacitor and a schottky diode. An Arduino Nano could then sample this voltage and discharge the cap after each pulse. Some simulation showed that 33nF or 50nF could be charged in a few primary cycles without drawing too much current. Apparently the Arduino's sampling capacitor is only 14pF so I don't think it'll drain the buffering capacitor and falsify the measurement.

I've been reading a bit more about the split MMC design and it seems like it's not as good as I thought (in fault cases): https://highvoltageforum.net/index.php?topic=294.0
At this point I don't even know if it's that much better than directly paralleling the IGBTs. A transformer might be an option too, but it's hard to find information on how to design it...

Tell me what you think!

Best regards,

V-Troxi

[Anders Mikkelsen]

For the current transducers, the Tamura would probably be fine, but the dynamic behavior is so badly specified (only a vague di/dt rise time specified) that I would prefer something with better documented behavior. The ICE part is meant for busbar mounting, and I would be a bit worried about stray field rejection and sensitivity deviation depending on your busbar geometry vs. the reference case. I would consider something like this https://www.digikey.com/en/products/detail/mornsun-america-llc/TL300-D1C/18735421 or https://www.digikey.com/en/products/detail/lem-usa-inc/HASS-200-S/1680530 , with preference to the Mornsun part.

For comparing devices, the datasheet current rating is pretty much meaningless, it's basically the current the device can run at with the package immersed in boiling freon without exceeding the maximum junction temperature. It does not consider realistic cooling systems, and it does not consider switching losses, so it's useless for comparing devices in *SSTC applications. The main issue is that IGBTs have much higher switching losses than IGBTs, and soft switching only helps to a limited extent due to effects like channel forward recovery. The best practical comparison I have found is from the paper "The practical use of SiC devices in high power, high frequency inverters for industrial induction heating applications", because it considers both resonant operation and frequencies in the range where QCW coils operate, I've attached a figure here:



This is comparing 300 A class SiC MOSFET bricks with 300 A class fast IGBT bricks, and even with three times as many IGBTs, you get less than half the output power at 400 kHz. There will not be a factor six improvement for pulsed coils, as MOSFET conduction losses rise quicker than those of IGBTs, favoring CW operation, but I would not be surprised if you get a factor 3 improvement, i.e. three times the amount of power for a given device current rating.

SiC device performance peaks at higher voltages, so you get better value from using 1200 V devices and much higher bus voltage. Both Steve Ward and Jan Martis' SiC QCW designs run at 800 V bus. Looking at existing designs gives a good idea of how much you can get out of a given device size. Steve Ward's 3-phase QCW only used two 21 mohm 1200 V MOSFETs to drive each coil, and that's using frequency detuning which is even more lossy than phase shift control.

[V-Troxi]

Thanks again for the input!

From your reply, I'd guess that you would build a single SiC full bridge and run at a higher voltage of 800V instead of 325V?
My buck IGBT is rated for 1200V so that would work, but I would have to replace the bus caps which are currently rated for 500V max.
I would also need to construct a boost converter or use a simple voltage doubler to get 650V.

What is the 300A SiC brick you've mentioned? Is it really fast enough for 400kHz operation? Most beefy SiC modules that I could find had higher gate charges and input capacities of more than 20nF (my current IGBTs have 5nF).

I've seen a lot of QCWs with multiple parallel SiC bridges online (by Jan Martis, Crazy Electronics, Tesla Explorer...) and that's why I was thinking of paralleling multiple TO247 FETs too.
And I'm still having a hard time believing that a single SiC bridge (with lower current capability) would improve the robustness of the inverter that much.

Yes, I could run at a higher voltage and increase the impedance of the primary to reduce the current, but I didn't actually plan to change the power supply stage (buck) that much.
If I could find a fast SiC brick with a relatively high current capability, that would be great!

I really want the new inverter to be robust and have a large safety margin!

Best regards,

V-Troxi

[V-Troxi]

If I'd figure out how to use a transformer for current sharing of two IGBT bridges, what would speak against this approach?
I know the switching losses are higher for IGBTs, but each bridge would be seeing less current than the current single bridge.

From what I've been reading, the most easy to drive SiC-MOSFETs are cascodes (which are (only?) manufactured by Qorvo right now) and they are still more sensitive to gate over-voltage than IGBTs which would make driving with a GDT more difficult.

I would really like to know what you guys think is the best approach!

Best regards,

V-Troxi

[davekni]

IXXN110N65C4H1 looks like a very capable fast IGBT.  I'd go with paralleling.  You could parallel pairs of IGBTs for each switch to form a single H-Bridge using 8 IGBTs total.  I think that is more common than paralleling separate H-bridges.  Though as you mention, using two H-bridges does allow splitting MMC, which helps force current sharing.

BTW, my ~80kHz DRSSTC uses 10 parallel IGBTs for each switch, 40 total for a single large H-bridge.  Positive temperature coefficient of Vce helps with current sharing, as does careful layout.  Each half-bridge is constructed with Vbus connected towards one end and output towards other end, making total copper plane resistance roughly  equal across IGBTs.  The issue with my particular IGBTs is a steep negative temperature coefficient of diode Vf.  This precludes my implementing pulse-skip OCD, as that stresses diodes.  IXXN110N65C4H1 diode is much better, so shouldn't be an issue.

Are you using the kelvin emitter connection of IXXN110N65C4H1 as intended, one for emitter current and other for gate drive return?  That will help minimize stress on IGBTs by cleaner internal Vge waveforms.  Well adjusted phase lead helps too, as does a good low-parasitic-inductance GDT.

GDTs are a problem for buck converter drive, especially at high duty cycle, unless outputs include capacitive coupling and DC-restore (ie. TVS clamps that conduct a bit at normal peak-to-peak Vge).  There are plenty of isolaters and isolated gate drive chips.  Most these days use capacitive coupling rather than optical.

This works well, but I want to improve the OCD that I've added. The current approach uses a CT but I think it's quite inaccurate due to the pulses being DC.
What is the best or standard way to do this? A shunt?

If the CT is in series with IGBT or diode rather than output, it can work fine, as there is a zero-current period.  (Except at 0% or 100% duty cycle.  0% isn't needed.  Max duty cycle would need to be limited to say 98%.)  CT secondary is connected with a diode in series.  That allows large opposite-polarity voltage pulses during zero-primary-current times, resetting CT core magnetic flux.  This use of CTs is common in commercial SPMS designs.

However, above CT use does add parasitic inductance in a non-desirable place.  For my old low-frequency QCW experiment, I'd made two parallel interleaved-timing buck converters capable of 350A each.  Used Hall sensors on outputs (in series with buck inductors) to minimize switching parasitic inductance.  Current sensing was to keep current balanced between the two converters, not just for OCD.  Since 400A sensors were hard to fine for reasonable cost, made my own using linear Hall sensor ICs and small gapped ferrite cores.  Sensors were ACS70310LKTATN-0015B-C from Allegro Microsystems.

My later more-normal QCW coil doesn't need more than 350A, so uses only one converter.  OCD is needed, but not linear response for current matching.  To simplify design, OCD uses a series resistor into an opto-coupler.  IR LEDs turn on around 1.2V.  Resistor power is high, but not too bad for low duty cycle QCW use.  (I'm actually using a red LED into plastic fiber, so around 1.8V.  IR would make more sense to reduce resistor power.)

[V-Troxi]

Thanks a lot, David!

BTW, my ~80kHz DRSSTC uses 10 parallel IGBTs for each switch, 40 total for a single large H-bridge.  Positive temperature coefficient of Vce helps with current sharing, as does careful layout.

Wow that's a lot of silicon .

I think I will go with a paralleled 8x IXXN110N65C4H1 bridge.
On littlefuse.com, it says, "Other qualities include a positive collector-to-emitter voltage temperature coefficient which enables designers to use multiple devices in parallel to meet high current requirements". This sounds good to me, and it matches with what you've said.

If I'd come up with a good bridge layout and a clean gate drive, would this be enough to guarantee good current sharing, or is there something else that I can or should do to improve/enforce this?
I don't want the new bridge to blow up due to improper current sharing .

Do you think that one GDT with four output pairs is enough to drive the bridge even with paralleled IGBTs?

I still have some "TX42/26/13-3E27" cores for a GDT lying around.
The last time, I just eyeballed 7 as the number of turns and got too much leakage inductance and dead time. Now I want to choose it properly, and I tried to apply the formula that I remember you'd provided once:
N = (V*dt)/(dB*A) = (24V * 1/(2*400kHz)) / (0.3T * 95.8mm^2) = 1.04

One turn seems a bit too low. I know I can add a few turns as a margin, so maybe I could go with 5 turns...?
Should I just try it out, or is there a more precise way or another rule of thumb?

Are you using the kelvin emitter connection of IXXN110N65C4H1 as intended, one for emitter current and other for gate drive return?

Yes, I was using the kelvin emitter for the gate drive return, and I'm planning to do the same again.

Interesting to hear that a CT can in fact work for a buck OCD, but I think it would be practical (for fault cases) if the OCD would still work at
100% duty cycle. Therefore, I've decided to use a hall-effect current sensor.

I'd be happy to hear what you think!

Best regards,

V-Troxi

[davekni]

If I'd come up with a good bridge layout and a clean gate drive, would this be enough to guarantee good current sharing, or is there something else that I can or should do to improve/enforce this?

Share a common heatsink, at least within each pair, to keep temperatures roughly matched.  This isn't too critical, as if one is better cooled, it will draw a bit more of the current due to positive Vf/T slope.  That's all I can think of.

Do you think that one GDT with four output pairs is enough to drive the bridge even with paralleled IGBTs?

My 8-IGBT QCW coil uses a single GDT, though followed by PFET buffer stage to make fast Vge fall times.  There is one small down-side to single GDT:  The emitter terminals of the IGBTs used for gate return need to be wired together.  If there is any imbalance in parasitic IGBT connection inductance, then the emitter return is the average of the two internal IGBT die voltages rather than each IGBT having its own return.  The careful low-inductance bridge layout will minimize this issue.  That's why I didn't worry about it.
Presuming you aren't including any buffer circuit between GDT and IGBTs, another advantage of two GDTs is net half parasitic (leakage) inductance.  (ie. same inductance, but feeding load of only one IGBT rather than two.)
If you decide to consider two GDT's, I'd instead wind one larger GDT with 8 twisted pairs.  Parallel one wire each all 8 for primary and use other 8 wires for IGBTs.  Same as winding two GDTs except they share one core.

I still have some "TX42/26/13-3E27" cores for a GDT lying around.
The last time, I just eyeballed 7 as the number of turns and got too much leakage inductance and dead time. Now I want to choose it properly, and I tried to apply the formula that I remember you'd provided once:
N = (V*dt)/(dB*A) = (24V * 1/(2*400kHz)) / (0.3T * 95.8mm^2) = 1.04

One turn seems a bit too low. I know I can add a few turns as a margin, so maybe I could go with 5 turns...?
Should I just try it out, or is there a more precise way or another rule of thumb?

That formula is sufficient to avoid core saturation.  Hopefully I mentioned in that tutorial that magnetization current load on driver needs to be considered. 1 turn would be 6.7uH, for 30uVs/6.7uH=4.5A on first startup half-cycle.  Would settle to +-2.25A.  Probably OK, but I'd suggest 2 turns (or 3 at most).  2 turns increases inductance 4x, so 1.1A at startup down to +-0.56A operating, plenty low for UD2.7 to handle.  Of course, keep GDT leads as short as possible.  Each cm of lead length adds as much parasitic inductance as does a cm of winding length.

Interesting to hear that a CT can in fact work for a buck OCD, but I think it would be practical (for fault cases) if the OCD would still work at
100% duty cycle. Therefore, I've decided to use a hall-effect current sensor.

I'd be happy to hear what you think!

Yes, that's what I chose too, both for handling 100% and to minimize buck switch parasitic inductance.