DRSSTC Performs

[ChrisBlis]

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Teslacoil performs now.

[davekni]

Great to see you are well past 1cm!

[ChrisBlis]

Thank you for your help David Knierim.

The problem was wrong resonance tuning to 100kHz instead of actual 220khz. Measuring offered different frequencies and I went with the lowest one.
Never the less due to looking for failure at other parts allowed me to optimize the system.

Now the primary circuit resonates at this frequencie too.

Should I adapt the 1nF feedback capacitor at the driver komperator to a lower value?

[davekni]

Unusual to find a spurious lower-frequency resonance when testing your secondary.  There are often higher-frequency modes.  I can't think of anything that would create a false low-frequency mode (ie. 100kHz when actual is 220kHz).  For future reference, the JavaTC program will generate a close estimate, making it easy to find actual frequency with a narrow search.

Yes, at 220kHz, I'd suggest 470pF for 330pF for C33 comparitor feedback capacitor.  It is clearly working at 1nF, but startup at each enable pulse should be more reliable with a smaller capacitor.

You are welcome!  Glad that my suggestions have been useful.

[ChrisBlis]

Should it be safe to go up to 1khz in frequenzy of on pulses?

[davekni]

Higher repetition rate depends on heatsinking.  If IGBTs are staying cool enough, increase the rate.

[ChrisBlis]

Is there some point of repetition rate which I should never exeed?

Or a rule a thump for max duty cycle and repetition rate?

[davekni]

I don't know any rule-of-thumb guides for duty cycle or repetition rate.  Other's here may.  Some coils can handle the maximum power available from the line cord.  Others overheat before getting that high.

[Mads Barnkob]

Is there some point of repetition rate which I should never exeed?

Or a rule a thump for max duty cycle and repetition rate?

I think there is a unofficial limit on on-time from 0-300 uS and 0-200 BPS that originates from the first DRSSTC interrupter design that Steve Ward released. It has been copied a lot ever since and has thus resulted in a kind of standard settings that ANY standard Universal Driver 1.3b-2.1b DRSSTC should be able to survive, given that it has been properly designed. When you get up into "new age" DRSSTC drivers with pulse skip, free-wheel, QCW, phase shift etc. its a whole other story because there are measures in place to mitigate very long on-times.

[ChrisBlis]

I am only able to go for 20us on time before the OCD detects overcurrent.

Did I anything wrong since you speak from 300us on time? Resonance frequenzy is at 220kHz.

My OCD is set to 180A at Fga65n60smd IGBTs.
I heart it should be possible to go for 250-300A is this still reliable and safe?
I use the UD2 driver without phase lead.

Because I want to play music with repetition rates up to 1000khz it my by wise to keep some space room?

[Mads Barnkob]

I am only able to go for 20us on time before the OCD detects overcurrent.

Did I anything wrong since you speak from 300us on time? Resonance frequenzy is at 220kHz.

My OCD is set to 180A at Fga65n60smd IGBTs.
I heart it should be possible to go for 250-300A is this still reliable and safe?
I use the UD2 driver without phase lead.

Because I want to play music with repetition rates up to 1000khz it my by wise to keep some space room?

Did you check you OCD trip limits with a injected signal from a signal generator, to confirm that it actually trips at the settings assume it does?

How is you coil tuned? Tripping at 20 uS tells me it could only result from serious de-tuned primary circuit or a short-circuited primary circuit/inverter.

[ChrisBlis]

I use 2.5mm house wire for then primary coil and lead wires. Insulation problem?

Fres secondary is at 220kHz. I tuned the primary circuit to this frequenzy as well.

I get with a 55nF tank cap and a 180A current limit a arc lengt of 50cm. Should this System give more?

I use a 160x40mm torus as topload. Maybe therefore the drained energy from the primary circuit is limited?

No i did not check the current limiter with a function generator. Is failure realy that likely?

[davekni]

Checking current is easy.  Scope across the CT feedback burden resistor, 51-ohm resistor R1 in the UD2.7 schematics.  See how high the voltage rises during your maximum 20us on-time.

JavaTC is very helpful in determining design parameters and what may need changing.  50cm seems reasonable for you coil, although more may be possible.  55nF at 220kHz is only 13-ohms impedance.  I'd guess that you need more primary turns and lower MMC capacitance.

[ChrisBlis]

The current goes up to 200A in the 20us.
Maybe I should really increase the impedance of the primary circuit.
But ist 20us still a realistic on time, or may there be another failure?
I now tuned the primary to about 220kHz. Should I instead go with 200khz?


https://youtube.com/shorts/OwJtmGp0jmE?feature=share
Any guess from where the pops at the beginning of the video come from? Maybe because of electromagnetic feedback?


Thank you for your help, David Knieriem and Mads Barnkob.

[davekni]

At 220kHz, 20us is 4.5 cycles.  My DRSSTC ramps up to start arcs in about that same number of cycles, but doesn't hit OCD then.  Obviously 20us is working.  I expect that higher primary impedance allowing for longer on-times will improve performance.

Yes, you could try 200kHz or 210kHz.  Experiment to see what works best.  Or increase impedance first then experiment with frequency.

Would need scope captures to make any reasonable guess on the pops.  Perhaps some erratic power-up behavior (not disabled as power comes up) causing short enable pulses that don't quite make arcs.

[ChrisBlis]

Scope shot current primary.
Why do the current spikes acour? Maybe this is the reason for the pops in the video?

[davekni]

The short ~5us on-times may be making the pop.  5us may be long enough to make sound, but not an arc.  The spikes are unlikely related to sound.

The spikes are almost-certainly caused by IGBT switching slightly after current zero-crossing.  Increasing phase-lead (more inductance for L1 in the UD2.7 schematic) will move the spike earlier.  Once it is before current zero-crossing, the spike will get much smaller too.  That's proper phase lead.  Your H-Bridge will be more robust with phase lead and the resulting softer switching producing less spiking.

Edit:  One more note:  Use a longer enable pulse, about your maximum 20us, for adjusting phase lead.  Phase may change some at high current relative to the low current of this short enable pulse.  If the glitches are earlier in the current cycle and lower amplitude at high current, then you may not need any adjustment.  Proper phase lead is important at the high current end of the pulse, less so at lower currents.