Author Topic: Current buffer design  (Read 301 times)

Offline prabhatkumar

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Current buffer design
« on: November 07, 2022, 06:57:58 PM »
Hi everyone,
I am in process of designing a gate driver using a pulse transformer for FGH40N60SFD for building a full bridge. Earlier, I had used the FDS4559 dual N-P channel FET as a buffer after my gate driver.
But, now I am out of parts for the dual N-P channel FETs. I have ordered them but its going to a while for them to come. Meanwhile, I was wondering what are the merits/demerits of using a MOSFET based current buffer against a good old BJT NPN-PNP current buffer. The BJTs seem to be much easily available locally and hence I was wondering about using them with my gate drivers.
I am not sure if this is a right observation, but most optocoupler based gate drivers like the HCPL-316 etc. tend to use BJT based current buffer.
I am also interested in the design of the BJT based current buffers like selection of base resistance RB, and other resistances which are absent in a MOSFET based current buffer.
I am attaching a reference current buffer(lone oceans labs 'brick driver' and 'Avago application note' for whose resistance values I am interested in knowing and also why they are even used at such positions.
From lone oceans schematic, I am interested in the calculations of values of R3 and R2. RG1 and RG2 are, I believe, standard resistors for the turn on and turn off of the IGBTS. Also, what is the significance of R2 here? I have not seen this resistor in many current buffer design, at least not in the Avago application note
Please give me some reference or else some insight into this topic. Thank you
« Last Edit: November 07, 2022, 08:18:48 PM by prabhatkumar »

Offline davekni

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Re: Current buffer design
« Reply #1 on: November 08, 2022, 04:42:37 AM »
Quote
Please give me some reference or else some insight into this topic.
Certainly BJT emitter-follower buffers can work.  I recently purchased a few BJT PNP/NPN pairs for such use.  (Since changed my short-term plans, so won't be using BJTs for a while.)

One consideration is that driver chip prior to BJTs must be full voltage.  Many of the drivers such as used as in UD2.7 aren't capable of 24V.  If 15V drive is sufficient, no issue.

Other consideration that comes to mind:  Schematics shown have a possible issue depending on rise/fall times and gate capacitance.  A fast input to BJT buffer and high IGBT gate load can cause excess reverse Vbe on BJTs.  Typical Vbe reverse limit is 5V, as in parts listed in schematics you show.  May or may not be a problem depending on exact values and driver chip used.  (Vbe reverse breakdown may not cause immediate failure, but can degrade BJT current gain over time.)  One option to avoid this issue is to remove emitter resistors.  Use standard diode/resistor combination on IGBT gates instead.  Only down-side of this option is one extra diode drop.  Quiescent off-state (ie. between enable pulses) clamps IGBT Vge to two diode forward drops rather than one.
David Knierim

Offline prabhatkumar

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Re: Current buffer design
« Reply #2 on: November 08, 2022, 05:34:33 AM »
One consideration is that driver chip prior to BJTs must be full voltage.  Many of the drivers such as used as in UD2.7 aren't capable of 24V.  If 15V drive is sufficient, no issue.
From what I understand, why is there a need of full output voltage at the output of the driver, if we use a different VCC level on the driver chip and the BJT current buffer, like how Gao does in the UD2.7 in his mosfet buffer?I really dont mind this since I will be using 15V as you said.

Also please can someone throw some light in the calculation of the base resistance ? The thing which is confusing me the most is the R2 resistor in Gao's schematic, Since its not there in many current buffer designs.
I don't seem to find much about this buffer circuit even on the internet. This circuit is called a BJT current buffer right? Please correct me if I am wrong.
Thank you
« Last Edit: November 08, 2022, 05:43:49 AM by prabhatkumar »

Offline davekni

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Re: Current buffer design
« Reply #3 on: November 08, 2022, 06:27:06 AM »
Quote
From what I understand, why is there a need of full output voltage at the output of the driver, if we use a different VCC level on the driver chip and the BJT current buffer, like how Gao does in the UD2.7 in his mosfet buffer?I really dont mind this since I will be using 15V as you said.
Easiest way to understand is with simulation (LTSpice or other).  Emitter-follower (and source-follower) circuits provide current gain but no voltage gain.  Voltage gain is 1 (actually slightly less than 1).
David Knierim

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Re: Current buffer design
« Reply #3 on: November 08, 2022, 06:27:06 AM »

 


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