UD2.7 GDT problem

[endi007]

I built a UD2.7 driver based on material from https://www.loneoceans.com/labs/ud27/
I have a problem with the signal on the GDT. Without a transformer, everything looks fine. I give the signal from the generator to the feedback input.
The GDT output is loaded with a 10 ohm resistor. Core made of 3E25. I tested a different number of turns 5, 15, 30. The effect is the same all the time.

For 100kHz it looks like this:



For 50 kHz like this:




The lower the frequency, the worse the signal waveform is. Only at 220 kHz does it begin to look correct.



Still, it's not perfect.
When I skip the capacitor C30 and C31 and connect the GDT directly to the MOSPHET, the waveform is correct. The same happens when I replace the C30 with a large 200uF capacitor.



I made Ud2.7 in the same way as on the website. I have not made any modifications. Why doesn't it work?


PS. to the current GDT:

[endi007]

I decided to connect a IGBT transistor as a load instead of a resistor and the results improved. It seems that for the system to work properly in this configuration,  transistor capacitance is needed. Resistance alone is not enough. But now I have another problem. In certain Ton time settings, there is an ugly tail behind the signal.



The problem is eliminated by mounting a resistor of about 100 ohms with a GDT.



Is it normal? Should the driver not eliminate it by itself?

[Mads Barnkob]

You waveforms looked fine all along, I do not see any problems, but as you also conclude, you need to see the waveform with the actual gate load. Else its impossible to adjust the gate resistor to damp overshoot.

Check out this great guide on GDT waveforms: http://www.richieburnett.co.uk/temp/gdt/gdt2.html

Slightly sloping tops and bottoms to waveform.

- The tops and bottoms of pulses droop slightly towards zero,
- Caused by low primary inductance. Too few turns on the drive transformer,
- This is not a problem as long as the amount of droop is less than a couple of volts,

Add a few more turns to the primary and secondary windings to reduce the droop.

Regarding the weird artifacts/noise, could it just be a trigger issue and its "flickering" signal dying out if the drive is cut on half a pulse?

[endi007]

Noise on "Ton" change. It is bigger when Tone is low. Look like this:

30uS -> good
35uS -> noise
40uS -> noise
50uS -> good
60uS -> noise
70uS -> good
80uS -> noise

The 100ohm resistor in parallel from GDT solves the problem. (I have a generator connected to the feedback input). No noise can be seen in the driver on the UCC,
they only appear on GDT.At some frequencies it can have a large amplitude that can open / activate transistors.



Maybe the problem is using  the generator instead of the coupling?

[davekni]

I decided to connect a IGBT transistor as a load instead of a resistor and the results improved. It seems that for the system to work properly in this configuration,  transistor capacitance is needed. Resistance alone is not enough.

Transistor capacitance is not needed.  The waveform droop in your initial scope traces is due to the resistor load.  The resistor draws current for the entire high or low time, charging/discharging C30 and C31.  Real gate loads don't conduct past the transition time.  No load would look fine too.

Maybe the problem is using  the generator instead of the coupling?

Are you using another generator for the enable pulses?  Or are they from an interrupter?  After the enable pulse ends, there should be no way for the generator feedback signal to create such noise.  My guess is that the driver chips are the wrong part (non-inverting instead of inverting), or that the AND gate is mistakenly using a NAND gate instead.  That leaves the GDT inputs floating between enable pulses.  Scoping the driver chip outputs will show if they are high between enable pulses as they should be.  (AND gate outputs low, inverted by the driver chips.)

[endi007]

Ud2.7 looks like this:



I have a function generator connected to the interrupter and feedback input. Integrated circuits I used are:
- SN74HC74D ( D flip/flop)
- 74HC08D ( and gate)

It seems that the extra (passive) capacity after the GDT is turned off creates oscillations that dampen the attached resistance.

[davekni]

It seems that the extra (passive) capacity after the GDT is turned off creates oscillations that dampen the attached resistance.

I'd agree, except that the UD2.7 output should clamp any GDT signal between enable pulses.  Either the signal-generator input to enable is picking up noise from your wiring or there is an issue within the UD2.7.  What markings are there on the driver chips (the parts that come after the 74HC08D)?

[endi007]

The mileage at the output of the UCC ( numer 27424 7CM ) looks like this:



On the mosphet Gateways (1L34BC FDD 8424H ):

A:


B:


On the GDT primary page, like this:

A:


B:


The video presents the problem when changing the Ton:

[davekni]

The mileage at the output of the UCC ( numer 27424 7CM ) looks like this:

That is the problem.  UCC27424 is non-inverting.  UD2.7 is designed for an inverting driver, UCC27423.  The driver chip output should be high between enable pulses.  Your scope trace shows low between enable pulses (wrong).  Low between pulses is exactly what a UCC27424 driver chip would produce.

[endi007]

 

That was exactly the problem. For test I connected the UCC input through the 74AC14 (inverting) gate and the oscillations disappeared.
It's not perfect. Maybe my test GDT is lame.  I will order the correct chips and go back to testing. Oscillograms on GDT loading by mosphet gate.

[davekni]

The low-amplitude low-frequency (~3kHz) waveform after enable ends is normal, a resonance of C30 and C31 with GDT inductance.  Are you back to normal values for C30, C31, and R24 (2.2uF, 1uF, 15ohms)?  The purpose of C31 and R24 is to damp that resonance.  Yours is lasting longer than I'd expect.  Amplitude is low enough that it should not cause any issues.