Current sharing in QCW inverters

[TDAF]

Exactly how does transformers or Split MMCs force the bridges to share current??

[Steve Ward]

Transformers:

Each transformer primary gets its own inverter.  The secondaries are then wired IN SERIES (this only works in series).  Since the secondaries are in series, their currents must be equal.  If the secondary currents are equal, the primary currents must therefore be equal.  Even if the inverters output slightly different voltage (maybe your bus wiring has unequal resistance or whatever) the currents will be the same, but their power contributions will be proportional to the voltage.  Essentially you are putting the inverters in series, rather than parallel.

Split capacitors:

Considering only currents at the resonant frequency, the capacitors represent the impedance of the tank circuit which is significant, so it's pretty safe to assume that the current through each section of the capacitor will be close to equal.  Variations in inductance making these connections can skew the balance some as the impedances add (complexly, however).  When using split capacitors and full-bridge drives, you should use what looks like "equi-drive" configuration, where MMC caps are placed on both sides of the primary, or else you are forced into directly connecting h-bridge outputs together which is no good.  The number of caps on each side of the primary need not be equal, but ideally they would be so that the capacitors offer maximum impedance.

If this idea still makes no sense, consider the alternative which is directly connecting bridge outputs together with some sort of wires or whatever.  The impedance of the H-bridge is tiny (if you short circuit it, you get huge currents till it fails).  The impedance of the capacitors is usually several ohms, so its very much like how paralleling transistors often include some sort of series resistor with each parallel part to help "even out" the resistance of each parallel branch and force a more uniform current distribution.

This scheme is not as fool-proof as the transformer scheme.  If there were, for some reason, a mismatch in switch timing (or if a bridge leg fails to switch) then the capacitor impedance to the very fast switching voltage is pretty much zero and you will see "shoot through" currents between bridge legs.  What i mean is, imagine 1 bridge output switched hi, but the other "parallel" one was still low, you are now applying 2 different voltages to the same node in your circuit, and if the impedance between those voltages is small (remember, capacitor impedance approaches 0 at very high freq) then currents are big.

[Hydron]

This scheme is not as fool-proof as the transformer scheme.  If there were, for some reason, a mismatch in switch timing (or if a bridge leg fails to switch) then the capacitor impedance to the very fast switching voltage is pretty much zero and you will see "shoot through" currents between bridge legs.  What i mean is, imagine 1 bridge output switched hi, but the other "parallel" one was still low, you are now applying 2 different voltages to the same node in your circuit, and if the impedance between those voltages is small (remember, capacitor impedance approaches 0 at very high freq) then currents are big.

This does concern me for the coil I am building - I have done some simulations and the results aren't pretty if one half-bridge fails for some reason.
I plan to try and do some sort of sensing to shut everything off if there is a fault like this (potentially by looking at current or voltage difference between half-bridges - I have a separate CTs for each so have a few options for how I do it).
I also am looking at how to limit fault current from any failure so that I'm not dumping several kJ from the main storage caps into a failed IGBT - am currently looking at a simple DC rated fuse, or potentially using a low-VCE(sat)/Rds(on) IGBT/MOSFET as a fast switch for reacting to a fault situation (in this case with more flexibility than a simple fuse).
Steve (and others) - any suggestions/ideas on either of these issues would be welcome!

The other question I have for Steve is regarding the impedance of his transformer coupled coil - I'm interested in what the primary tank values are and what the transformer ratio is to see what the tank circuit impedance looks like to each half-bridge (and to compare it to what I have, which has no transformer but a relatively low tank impedance for a QCW coil).

[TDAF]

I'd like to ask,
Why don't the transformer cores saturate??

[Steve Ward]

Why don't the transformer cores saturate??

Saturation of a transformer happens because there is too much magnetic flux in the core.  Flux is proportional volts*time/number_of_turns.  For a simple inductor, the current is proportional to volts*time/number_of_turns... which means flux is proportional to current.  Now for the "confusing" part... when looking at a transformer, there is another coil coupled in there (the secondary) and it's current interacts with the primary coil current to give a resulting flux in the core.  Any secondary current will generally cancel out the additional primary current, and so despite operating at a high level of current, the magnetic flux in the core is the same as if there were 0 secondary current and only the tiny "magnetizing current" that would be in the primary coil as its energized by the source voltage. 

Steve (and others) - any suggestions/ideas on either of these issues would be welcome!

Fuses might be fun to try.  I thought about protection circuits of all kinds... you just listed out most of them.  At the end of the day I didn't bother with any of it and focused on making sure i was not stressing components to the point that a failure would be likely.  Of course, if you look at my flickr you can see the gnarly results from when this fat coil DID have a failure.  My take on that was that it incurred more damage due to plasma/sparks emitting from failed IGBTs to non-failed ones, spreading the failures out further.  I would look at ways of mitigating the propagation of failures.  Either add more distance between transistors, or consider some sort of materials that might be able to withstand the blast (think about how IGBT modules use the silicone goo to contain the plasma/sparks). 

I use a big IGBT as a "circuit breaker", like you describe, for some of my motor drive research to reduce failure propagation on a drive that i built which crams 384 GaN mosfets into a 4"x2" cylinder.  The IGBT can interrupt the bus in ~1uS which limits the destruction to just the device that originally failed, rather than letting it spew plasma at all its neighbors which triggers more failures and destruction of PCBs and stuff.  Depending on the source inductance, this IGBT may need snubber capacitors across it so that it can safely open under fault current conditions without over-voltage.  It can help to use a high gate resistance so the turn off is slow... particularly with IGBT modules that have significant intrinsic inductance.

My buck inverter has current limiting as part of its digital control laws.  Unfortunately, feeding failed bridges with a 500A current limited source still makes for a lot of destruction, but the buck transistors were OK .  If i were so inclined, i'd program it to notice that the buck output voltage is low for too long despite high buck currents and that this is a fault condition which should turn everything off.

I'm interested in what the primary tank values are and what the transformer ratio is to see what the tank circuit impedance looks like to each half-bridge (and to compare it to what I have, which has no transformer but a relatively low tank impedance for a QCW coil).

I think the primary C is 13nF on the FAT coil.  The reflected impedance is such that i maximize each bridge's output current to ~75A, or 600A total for all 8 bridges.

[TDAF]

Any secondary current will generally cancel out the additional primary current, and so despite operating at a high level of current, the magnetic flux in the core is the same as if there were 0 secondary current and only the tiny "magnetizing current" that would be in the primary coil as its energized by the source voltage. 

WHOA!!
That's some wonky-ass science right there!!

[Paultesla]

Steve is correct. The flux in the core is about the same off load as on load. Transformer cores saturate from too many volts per turn of winding, or a DC voltage applied for too long.

Paul

[Hydron]

I think the primary C is 13nF on the FAT coil.  The reflected impedance is such that i maximize each bridge's output current to ~75A, or 600A total for all 8 bridges.

That's a similar per-device current to what I hope to run in my coil, though I can't be sure yet as I've had to current limit the prototype single bridge (chickened out at the 225A Icm rating of a 75N60!). I've held off ordering the PCBs to expand it to the full quad-bridge design as I'm worried about large Vce spikes I'm seeing when hard-switching-off the IGBTs, so some design review is in order before I can get the final design up and running and find out current it'll actually run at without artificial limits.
In order to get larger currents through the system without going for a transformer I've used a much larger MMC capacitance (24.8nF) for a lower impedance tank - time will see how well it works but in bench testing I have gotten some promising sword-sparks without blowing anything up.

As for protection, having looked at some fuse datasheets I think I'll go with the IGBT bus switch method plus a fuse for backup - I'm using phase-shift modulation so can't isolate the energy source behind a buck converter. I do however have the IGBTs spaced further apart than you did (each with an isolated heatsink, so no kapton failure mode either), so hopefully cascading failure isn't such a concern, especially if I am able to sense one half-bridge go bad and E-stop everything before it spreads!

[profdc9]

I have been working on my own half-bridge board, maybe it will be helpful to give you ideas:



In lieu of having a four layer board, it uses extra jumper wires you solder to the board.  There's return current jumper wires for the high-side gates, and jumper wires between the two sides of the board.  The half-bridge boards could be combined into a full-bridge.

I think this hopefully should provide lots of local snubber capacitance at each bridge, wide traces, good overlap of the power buses with the device traces, and low inductance connections for the gates and between the low and high side for small DC and AC loop size.  All the devices on each side can have their collectors joined to the heatsink as well.  I think I've tried to incorporate best practices while keeping the board economical.

Dan

[Hydron]

Thanks for sharing the design, though I can't say too much just going off one picture, I do have a couple of comments:

- There will be significant current flow between the DC bus connections of 2 half-bridge modules like this (return current for the flow going through the primary circuit). Make sure that half-bridge boards are connected together with good sized wires, or put a full-bridge on each board. I have the same issue with my original design, though I'm thinking of doubling the board size to put a full-bridge on each PCB with a nice big plane for each power rail.

- The layout does not seem to minimise inductance between the Hi and Lo side connections to the bridge output. For a soft-switched design this is unlikely to be an issue, but in hard switching a substantial current needs to commutate between the IGBTs on one side (e.g. Lo) and the diodes of the other (e.g. Hi) with a large di/dt, which causes big voltage spikes across the IGBTs. I can see this on my design when hard switching high currents despite having the hi/lo side IGBTs close to eachother. In one test I moved them further apart (had 2 possible positions) and the problem got worse.

[profdc9]

Yes, the two boards probably have to be placed so that their power terminals are right next to each other.  Also, there's four jumper wires to be soldered between the lo and hi sides "Bridge1-Bridge1" "Bridge2-Bridge2" "Bridge3-Bridge3" and "Bridge4-Bridge4" to try to minimize the inductance between the two sides.  It's very hard to get all of the four signals (lo/hi/vdd/vcc) to be in one place without a four layer board, my solution was to add these jumper wires to add four  parallel connections for the current to low directly from lo to hi.

The blue wires are jumpered between the lo and hi side collector/emitters, the purple wires are return current for the hi-side gate/emitter drive.



Dan