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Messages - SteveN87
1
« on: June 20, 2023, 12:05:48 PM »
This problem goes away when I change innocuous things, Maybe not so innocuous - the ADC values are probably changing asynchronously to the state machine clock. This will eventually cause a metastable state in the state machine's registers and subsequent malfunction. The ADC values (and any other asynchronous inputs to the state machine) need to be synchronized to the state machine clock - preferably 2 levels of registers, given the cost of a 'stuck ON' failure at full power. The unconstained clocks/paths can be solved by adding a .sdc (synopsis design constraints) file to your Quartus project. A basic .sdc file would be (assuming CLOCK_50 is the 50MHz oscillator input on the de0-nano) : create_clock -period 50MHz [get_ports CLOCK_50] derive_pll_clocks -create_base_clocks derive_clock_uncertainty
There's plenty of .sdc documentation on the web, independent of Intel, but you shouldn't need much more than the above for a simple project.
2
« on: January 25, 2023, 08:35:49 PM »
I think your 100R feedback resistors should be connected to the bases of the driver transistors, not +5V.
3
« on: January 12, 2023, 01:06:06 PM »
The turns ratio of an ignition coil is more like 100:1 than 1000:1.
As connected, D5 will short out the back EMF (great for relay drive circuits, but not so good for this), meaning you'll get about 200V of spark voltage (you would be more likey to get a spark from the forward voltage - about 1500V). Probably just remove D5.
4
« on: March 07, 2022, 05:08:52 PM »
...Cap, at least in my fbs, is obviously connected to "ground" So the answer to my question "Have you connected the bottom end of the cap to ground?" is "no, the manufacturer has already done it internally."
5
« on: March 07, 2022, 02:07:03 PM »
Also not clear what you mean "bottom end of the cap to ground", Like this one:
6
« on: March 07, 2022, 12:35:15 AM »
I have a Sony flyback (from a Trinitron portable TV - sorry, don't know the part number) which has no capacitor - it produces a hissing arc rather than sparks.
Have you connected the bottom end of the cap to ground? How are you driving the flyback (e.g. ZVS, bridge, true flyback)?
7
« on: March 27, 2021, 12:35:55 PM »
Why not just use a UC3842? Ok, thanks - will look into that possibility. Edit: no advantage, will stick with original.
8
« on: March 25, 2021, 03:07:42 AM »
Wow Steve that's really cool! How long did it take you to come up with it and does the fet/IGBT need much heatsinking? Thanks, about a year - on and off. It started with 4 transistors in the driver part - managed to get it down to 3 in the end. The prototype in the picture has about 8 sq in of ali heatsink on the IGBT - didn't even get warm after a 1-minute run. Actually on a related note what is an acceptable switching device temperature for this kind of application? I assume peak current limiting cuts down on a chunk of the heating. I'm guessing R7 and R1 are parasitic resistances too. The datasheet should give a max junction temp - aim to stay below that by an amount proportional to the cost of the device Peak current limiting, yes, but more so - switching losses. R7/R1 - yes. The (Simetrix) simulator does allow entry of capacitor ESR, but it's buried 2 menus in, so I usually just add it separately unless it clutters the schematic.
9
« on: March 19, 2021, 05:04:28 PM »
I normally use an IGBT version, running off 24V. This is a MOSFET version of it, simulated in Simetrix. The transformer parameters are: primary inductance=100uH, turns ratio=100, k=0.92. Because it drives just a single primary, it can be used on more-or-less any ol' transformer, as long as the DC resistance is reasonably low. It's a really a "power monostable with inverting output" triggered by the current reaching a certain level and holding the FET off for a fixed time (enough to allow the drain voltage to swing back to zero). The key is that the turn off of the FET is independent of anything going on in the primary, so it can be turned fully off before the drain voltage starts to rise. The off time is set by C1 - 1.5nF gives about 20uS. The totem pole gate drive (reminiscent of old 74-series TTL) is "on" by default and uses the lower transistor, Q4, as the current sense and once triggered, the gate voltage goes low and Q1 reinforces the situation via C1 and R9. When C1 has charged up sufficiently, Q1 turns off, as does Q4 and the gate drive goes high again. C1 is discharged though R9/D1 etc and the process repeats. The zener regulator doubles as a delayed start to allow the main decoupling to charge fully - essential with this circuit when operated at high current. D1 helps it to operate as a delayed start rather than a soft start (we don't want the gate voltage to ramp slowly through the threshold when the peak current is set for (say) 10A). At low loads, most of the power is returned to the source - this can put a lot of ripple on the supply, so good decoupling is essential. Alternatively, separate supplies could be used for the driver and VDD. Peak current, Ipk, is ~= 0.7/R15 and peak drain voltage ~= Ipk * sqrt(primary inductance/C3) The operating frequency depends on the supply voltage, the peak current setting, the off-time setting, the primary inductance and the load. All things being equal, the frequency is lowest at no load, because the primary current is starting from a negative value. The frequency will be approximately twice that at loads where the maximum power is transferred. At higher (heading towards short-circuit) loads, the frequency will increase quite a lot as the primary inductance becomes the leakage inductance. For well-coupled transformers (k > .95) the circuit may start to operate in CCM at high loads. Here's an early prototype of the 24V/IGBT version driving an ignition coil/jacob's ladder. The larger arc at the top is occuring where the gap is about 8cm. It works very well with LOPTs too.
10
« on: March 19, 2021, 12:48:11 AM »
Could this work as a way to limit peak current? I know a dedicated SMPS IC would be best but as a quick and dirty protection method would it behave or just oscillate. Probably oscillate - but you can exploit that to make a self-oscillating circuit. I use such a circuit which I'm very happy with. I haven't posted it here for 2 reasons - 1) there doesn't seem to be much interest in true flyback drives these days and 2) it's an all-transistor circuit. I can post it if anyone's interested.
12
« on: February 20, 2021, 01:27:43 AM »
Your sim waveforms show that the capacitor has given you zero-voltage turn on, but not zero-voltage turn off. At turn off, there is high collector current - you don't want high collector voltage as well. Somehow the MJ15003 is doing a better job at turn off. Was literally going to get a collector current waveform by soldering a 0.1ohm resistor in there but my irons heating element just blew as I was heating it up to do so They pick their moments, don't they!
13
« on: February 17, 2021, 01:28:26 AM »
I'm starting to think the internal structure of the transistor might be critical, or maybe the turn off and storage delay parameters. Yes - because you have the resonant rise capacitor, you'll also have a resonant fall on the base - i.e. slower than the typlical circuit without the capacitor; so a device with good turn-off characteristics should be better. More turns on the feedback winding may help.
14
« on: February 16, 2021, 02:30:13 PM »
Maybe the magic of the MJ15003 is its decent current gain - perhaps the base drive is insufficient with the 2n3055 etc.
15
« on: February 04, 2021, 07:51:14 PM »
This one has an air 'tunnel': These PSUs are a treasure trove of re-useable parts.
16
« on: January 20, 2021, 08:40:45 PM »
OK. Got it.
17
« on: January 17, 2021, 02:20:09 PM »
I have a very similar unit to yours, marked "LASER HIGH-VOLTAGE" "HS-16-40W" The core is not gapped (and from the photo, it looks like yours isn't either), so it can't be driven as a true flyback. Also, mine has a full-wave rectifier and a built-in capacitor of about 240pF on the output. The primary is 3.3mH with 0.6 ohm DCR. Looks like it was intended for half-bridge drive from rectified mains.
I added a separate primary and a gap to the core and drove it as a true flyback (that's how I found it had full-wave rectification). The overall result was disappointing, because there was strong dielectric barrier discharge from the plastic casing to the core, and sparks rather than arcs on the output.
A ZVS driver would turn this into a nice HVDC power supply, but pushing it too far will likely cause that built-in capacitor to fail.
18
« on: December 11, 2020, 01:47:20 PM »
The AliExpress link doesn't work for me, but it looks like a Tesla Magnifier. With such a small 'extra' coil, the resonant frequency will be high (a few MHz) so the half-bridge circuit you found is a good candidate for driving it in CW mode.
20
« on: December 08, 2020, 04:04:27 PM »
I used a different simulator (Simetrix Elements) and got reliable oscillation too. Yes - food for thought on self-oscillating bridge circuits.
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