First SSTC build - some questions

[zytra]

Hi guys,

I've been building my first TC, which initially was going to be powered by a static spark gap.
I steered away from the SG/NST but kept the secondary, which in retrospect isn't a great idea considering SSTC are typically not as long (relative to their diameter).

I went with Loneoceans' SSTC2 circuit. I changed my primary design to a 12AWG wound tightly around the secondary.

The way I got the system working was by disconnecting the secondary feedback and feeding the input of the UCC27425 with a square wave from a signal generator. FYI The rectifier and the AC transformer are both running off an isolating transformer.

With no top load I got the coil to resonate at 299 KHz. With the two large half bowls (stainless steel) mounted, that frequency dropped to 174 KHz.

With roughly 60-65VAC on the output of the variac, discharges were roughly 5-6" long.

As interrupter I am using the second channel of that same signal generator (feeding the base of a transistor that turns an IF optic fiber on and off).

I am not quite sure why the feedback isn't working. I did try to reverse polarity on the feedback. But I haven't checked what the signal looked like on the oscilloscope, yet. I did read a post yesterday that suggested a 1K resistor should be placed before the clamping didoes, but I thought I would try the original circuit before "fixing" it. So I'll probably give this a shot tomorrow.


One question (the main reason I am posting this) though:

I read that TC's without feedback are not running as optimized because the resonant frequency tends to change depending on several factors. On my tests, I didn't seem to observe that behavior off the 10-15 minutes I was playing with it.

However, at some point the nice discharges I was getting (1ms pulses maximum, frequency being varied from 10 to 200 Hz roughly), stopped a heavy plasma came out. Current draw on the wattmeter (on the wall) increased significantly so I turned the variac down and turned off the system. Waited a little bit before turning it back on and it was still outputting plasma rather than discharges. I waited a little more, and after a while it was back to normal.

Can anyone help me understand what that behavior might be? Although I didn't try changing the frequency (as it was definitely outputting something, so it was at least fairly close to resonance), it did feel like something else was at play.

I didn't capture this on video, but if it helps I am sure I can eventually reproduce this tomorrow.

Cheers

[Mads Barnkob]

Hi Zytra and welcome to HVF!

Some pictures of your setup would be nice, much easier to help out from images than plain text.

Running a SSTC without feedback is not going to hurt it, as it should be designed for hardswitching in the inverter. I wrote a bit about this and some calculations in the SSTC design guide.

It sounds like your feedback is too weak or wrong polarity to drive itself. It could also be that the parasitic energy transfer from driving circuit is not enough to kick the coil going in the first place. You need to investigate this further with your oscilloscope.

What you call plasma, I assume that is Continues Wave mode, where it is no longer interrupted, so its running with output at every single cycle of its resonant frequency (or in your case, the frequency you are feeding it with the signal generator)

[davekni]

Yes, that Loneoceans SSTC 2 circuit has issues with feedback design.  The 0.1uF capacitor should be to the right of the diodes (on the CT side).  As drawn, it attempts to create DC voltage across the CT.  That will distort the feecback waveform and likely saturate the CT core.

Concerning plasma (interruption failing), that is likely some detail of you your signal generator is connected to the driver chip enable pin.  Perhaps signal generator amplitude is marginal for disabling the driver.  Scoping that path should show the issue.

[zytra]

Thanks guys.

The "plasma" I experienced is I think consistent with failure in the interrupter. As I mentioned I played with frequency and duty cycle a little bit and increasing the interrupter frequency (at a given duty cycle) tend to make discharges shorter (probably because the pulse length is shorten due to the duty cycle is being kept constant). And the "plasma" looked like what would happen at higher frequency.

I am not sure what caused the (temporary) failure (since it came back after a few minutes with the system off). I initially thought perhaps the signal generator itself was acting up due to RF (and its close proximity, it should have been further away) but in retrospect it would have probably acted up on both channels, hence messing with the resonance frequency I was feeding the driver due to the lack of a working feedback. Another device (too) close was the DC power supply that supplied the small PCB converting the output of the interrupter (signal generator) to fiber optic.

Next time it happens, I'll try to have the scope probing the output of the signal generator to see if anything looks abnormal, if not, then it's likely happening on the driver's end.


Dave, thanks for your comment on the feedback circuit (of the SSTC2). I had seen your comments in at least one other thread and my understanding was that the 1k resistor was the one on the wrong side of the clamping diodes but based on your reply it sounds like it's definitely more about the location of the cap rather than the resistor. Would there be any harm in adding another 0.1uF capacitor on the CT side? If so, that test could be done rather quickly.


Thanks again!

[davekni]

Yes, it's likely fine to leave the other cap in place.  To really make that circuit reliable, there should be bleed resistor(s) to define the initial state of feedback and a bleed resistor on the half-bridge to define it's initial state to the opposite.  Then the initial half-cycle at the beginning of an enable pulse will always create a transition on the half-bridge output, with the next half-cycle switching feedback states.  Or, as I was describing in another thread, a resistor across the first 74HC74 stage will make it self-oscillating, so that it will start up no matter what the initial state may be.  Then bleed resistors aren't needed.

[zytra]

Thanks Dave, I will add the capacitor before the clamping diodes and add a 1k resistor across pins 1 and 2 of the 74HC14. I'll report back when that's done.

Cheers

[davekni]

I suggest a larger resistor from pin 1 to 2, more like 10k.  That way the feedback signal can take over the self-oscillation reliably.

For best results, reduce the value of the existing 0.1uF capacitor on the HC14 input until the self-oscillation frequency is close to your operating frequency.  That will make for faster startup.  Something like 1nF instead of 0.1uF and 10k from pin 2 to 1 should get around 100kHz.

[zytra]

Thanks for the clarification, I'll give this a try shortly!

[zytra]

Quick update. I did not get to modify the feedback circuit yet. I started where I had left off and decided to see if I could reproduce the interrupter failure. And I spent most of my time trying to figure out why this was happening.

I think the issue relates somehow to the signal generator not being isolated. It should have been if it was only used as interrupter, but since I am using as resonator source the signal generator now shares a ground with the driver circuit. I'll verify this was indeed the cause tomorrow by using a separate signal generator for interrupter and resonator.

I confirm that you guys' guesses were correct. Whenever "it" happens, I was able to verify that the interrupter behavior was erratic - causing a high effective duty cycle on the enable pin - hence loading the system significantly.

More on both topics tomorrow!
Cheers

[zytra]

Hi guys,

I found an easy way to move the capacitor ahead of the diodes. I used a 3-pin header (I always use 3-pin rather than 2 pin because I feel like they sit better) for the feedback so all I had to do was invert pin 2 and 3 in my plug as luckily the capacitor was across pin 2 and 3 on the PCB. This effectively allowed me to have the capacitor before the clamping diodes. I also had to move the input of the 1k resistor from pin 2 to pin 3. Then added a10k resistor across pins 1 and 2 of the 74HC14. I reinstalled the Schmidt trigger in the DIP socket and that was it, feedback is now working!

Now I'll need to put my hands on one of those UD2.7c so I can use that coil as it was initially intended!

On a side note, using a separate signal generator for interrupter and resonator did not solve the interrupter signal issue. So it was not a ground issue, but simply that the signal generator (or PCB converting the electrical signal into an optical signal) was standing too close to the coil. After testing with 2 separate signal generators for resonator and interrupter, I pulled everything much further away and the issue didn't manifest again.

Thanks again for the help.

[zytra]

Here's a quick video of the result: https://www.youtube.com/watch?v=wMmnOF0bZLs

Sorry about the quality, it wasn't great to begin with but after the upload it's quite a bit worse.

Mosfets are running surprising cool.

Before I turn this in a DRSSTC I'll measure Vgs abd Vds, and I'd also like to take some current measurements.

Generally speaking I am trying to keep pulses under 1ms (100 Hz -> 10% max, 10 Hz -> 1% max, and so on). Does that make sense? Is there a method to experimentally estimate what a good maximum pulse duration might be?

Last question, is there a technical reason (besides SSTC being naturally not as challenging on the inverter) for SSTC not to fine tune phase lead and optimize for ZVS?


Sorry for all the questions!
Cheers

[davekni]

Two limits come to mind for maximum enable pulse width.  One is energy stored in the VBus bulk capacitor(s).  Unless pulse width is more than half a line power cycle, the energy for that pulse is coming from the bulk capacitor(s).  No harm in a long pulse, but performance may not be as expected due to sagging VBus voltage.

The other limit is more critical, the transient thermal capability of the IGBTs or FETs in the H-Bridge.  It's also harder to calculate.  For an SSTC that is (typically) not running in ZCS mode, switching (switch-off) losses are significant.  Switching losses are sometimes listed in data sheets, but must be extrapolated to your operating conditions (current, voltage, gate resistance).  Conduction losses can be estimated from on-resistance and RMS current.  (For IGBTs, look at the high-current end of the Vce vs. current plot and estimate an on-resistance from that point back to 0.  Won't be precise since IGBT V/I curves are not linear.)  Add the losses and compare with the spec's transient thermal impedance graph.

It isn't common, but ZCS is possible under certain conditions for SSTCs.  It's mentioned in this thread:
https://highvoltageforum.net/index.php?topic=1355.msg10042#msg10042
https://highvoltageforum.net/index.php?topic=1355.msg10073;topicseen#msg10073

Also, my QCW coil is running mostly like an SSTC in ZCS mode:
https://highvoltageforum.net/index.php?topic=1268.msg9330#msg9330

[zytra]

Thanks for the links.

Agreed, the first limit does not bring any concern of failure if the pulses are a bit long.

For the second one with no idea yet on how much much current is going through the primary, it will be difficult to do any estimation. I do have a thermistor installed to measure Tcase on one of the two IGBT's, and since that second limit relates to thermal impedance, would it be safe to use that temperature sensor to estimate if a pulse duration is acceptable or too high? Or would the sensor, and the user's reaction time would be just too slow to prevent damage in the case of pulse that is too long?

At the bottom right of page 5 of the datasheet ( https://www.onsemi.com/pub/Collateral/HGTG30N60A4D-D.PDF ) there's a total switching loss vs gate resistance for various Ice (which I'd suspect is RMS?). Would I estimate the power losses in W as the switching losses (in mJ) divided by the enable pulse duration? For example, assuming 7 ohm gate resistance and Ice of 15A, the energy loss would be 1E-3 J. Assuming a enable pulse duration of 1ms, the power loss would be 1W. I think I am missing something.

[zytra]

I managed to hook up the oscilloscope this morning.
Variac set to roughly 15VAC, interrupter settings were 40Hz and 4% duty (1ms pulses).

In yellow I have Vge, and in purple Vce. I am not sure what the high frequency ringing taking place on the collector is, but that doesn't look right.

[davekni]

A thermistor will be useful to see if your long-term duty cycle is too high and/or heatsinking is insufficient.  It will not be useful in determining maximum pulse width.  The time constant of heat getting to the thermistor will be seconds, not milliseconds.

For SSTC switching loss, you are interested in Eoff only.  Presuming the gate resistors provide sufficient dead-time, the IGBTs should always be turning on with 0Vce, so have no significant turn-on energy.  The current to use for Eoff is the current at the time of switching, not RMS.  (6.8 ohms may be a bit small to provide sufficient dead-time for TO247 IGBTs.  What parts are you using?)

The power during a burst is Eoff * frequency, where frequency is the Tesla coil operating frequency, 174kHz in your case.  1mJ adds 174W during a burst.  If conduction losses add another 126W, then total is 300W.  Look at the transient thermal impedance graph to see what duty cycle and pulse width would keep temperature reasonable at 300W.  0.3C/W would result in 90C rise at 300W.

The Vce ringing is likely caused by parasitic inductance in the VBus supply (50V here, 340V at full voltage).  You may need to add film capacitor(s) across VBus at the IGBTs, from low-side emitter to high-side collector, with short leads.  A picture or two of your half-bridge and wiring would be helpful.  If you want to minimize parasitic inductance, I suggest using copper planes instead of wires, as in this example I made last month:
https://highvoltageforum.net/index.php?topic=1324.msg9795#msg9795

The ringing may not grow linearly with bus voltage.  But 300V peak at 50Vbus is enough to be concerning - may fry IGBTs at higher VBus.

[zytra]

Thanks David for the clarification on losses.

I put everything on DIY'ed bus bars, but I still have (too many) wires between these bus bars, IGBT's, large bus capacitors. Even the GDT secondary wires are too long. On the next one, I'll definitely do a better job - it was the first time and I really went off the schematics.

My circuit is close to that of the SSTC2 made by Loneoceans. I did add some protection to the IGBT namely a pair of zener diodes in opposition and a TVS diode between gate and emitter (both of those are absent from his design). The 6.8 ohm gate resistor is protected with a schottky diode instead of a regular diode on Loneoceans' circuit.


I also took some current measurements (1V = 1A) on that blue/third channel.

[zytra]

Quick update, I added a 1uF film capacitor (measured 25 mohm on the LCR @ 150kHz).
I did significantly improve Vce, however, both current and Vge traces seem to be not as good.

[davekni]

The ring frequency increased due to the lower inductance.  Ideally it gets above the switching speed of the IGBTs, so the parasitic frequencies aren't excited.

Looking at your layout, I suggest a couple other relatively-small changes to this build.  First, add a short wire under the lead end of the IGBTs joining the center of the half-bridge (collector of lower IGBT to emitter of upper IGBT).  That will complete the short current loop through IGBTs and your just-added 1uF capacitor.  (Is that capacitor soldered directly to the IGBT leads, not back on the bus bars?)  Second, twist together each pair (gate and emitter) of output wires of the GDT all the way up to the IGBT, soldering directly to the IGBTs as close to the package body as is feasible.

Hopefully with those changes, this first built will be robust enough to run for a while.

[zytra]

Thanks for the tips. I'll give this a shot now.
Yes the film capacitor is soldered on the IGBT leads.

The GDT leads going to the gates are soldered directly on the IGBT as well, however the other ends are going to the bus bar as I find it difficult to do a clean job when soldering multiple wires on one tiny lead. And to be frank, I was mainly thinking it would be easier to swap IGBT in case of failures. But what you say makes sense and I'll do that, with the oscilloscope hooked up it should be easy to make a decent side by side comparison.

Since ringing increased a bit would it make sense to increase the size of the gate resistor?

thanks!

[davekni]

Yes, I suspect a larger gate resistor would help.  Some designs add a smaller resistor in series with the diode (or in series with both the diode and other resistor, so in series with the gate connection).  That slows down turn-off a bit, which can also help.

Yes, soldering multiple wires to the IGBTs has down-sides.  The parallel-plane layout helps with that, but GDT wiring still needs to connect separately to the IGBTs.  The reason for connecting GDT emitter connections directly to the IGBT is that it keeps the high-voltage output ringing (mostly) out of the gate.  Part of that ring signal is on the emitter wire from IGBT to bus-bar.  That part gets added to gate voltage with the remote GDT return connection.