UD+ debugging (randomly skipping pulses)

[AstRii]

Hello!

I have a weird issue with feedback on one of my coils with Phil Slawinski's UD+ driver. The schematic of the driver can be seen here https://www.classictesla.com/pslawinski/UD2%20CPLD.pdf

My issue is that sometimes the driver skips an interrupter pulse. It tries to begin pulse but quickly triggers protection of the driver and sets Fault high.
I have tried to measure the output of the TL3116CD comparator here:

This is what I've measured:

Sorry for the terrible ripple, it's just interference from primary coil picked up by probes.
The red is the interrupter pulse which goes low as expected.
Yellow is the "ZCD" test point. On this above picture the pulse is alright.

However sometimes (randomly) the ZCD output goes high before even interrupter signal starts:


And when this happens, it tries to start up but it fails:


It's quite hard to capture as it's seem to be happening randomly (no matter the BPS, no matter the bus voltage).

Here I've made a short video

I have the UD+ board already bolted to the coil structure and wanted to seek help first, before I disasemble it. Did anyone had/have similar issue or do you have some ideas on why the TL3116CD goes randomly high before interrupter pulse?

Thanks for any advice!

[davekni]

Unlike UD2.7, UD+ has no DC bias on FB comparitor input.  State between bursts is indeterminant.  I don't know UD+, but will presume the CPLD logic is similar enough to UD2.7.
Do you have a resistor across H-bridge outputs?  If not, bridge may be starting in same state as FB comparitor occasionally starts (high output).  Enabling then generates no startup transition on H-bridge.  I'd guess UD+ is working fine.  H-bridge output needs to start centered (0V differential) so that either polarity of initial half-cycle starts oscillation.

[AstRii]

Hi Dave, I actually didn't have resistor on H-bridge output, however I added 22k resistor and the problem still persists. My MCC has 50nF, that's 1.1ms time constant together with 22k resistance. Should be quick enough for my roughly 100BPS@170us test.

[davekni]

Hi Dave, I actually didn't have resistor on H-bridge output, however I added 22k resistor and the problem still persists. My MCC has 50nF, that's 1.1ms time constant together with 22k resistance. Should be quick enough for my roughly 100BPS@170us test.

I'd suggest scoping H-Bridge output.  Or at least measure voltages with a meter with Vbus applied and idle.  Perhaps one IGBT is slightly damaged and conducting slightly when "off".

If that shows nothing, will require more detailed testing.  Seems unlikely, but if gate driver for one side of GDT primary is not being disabled between interrupter pulses, I think that could explain symptoms.

Not what I'd recommend, but you could patch the issue with a weak pull-down (~100k) on + input of comparitor, forcing idle state low.

[AstRii]

I'd suggest scoping H-Bridge output.

I have measured whole bridge, all transistor's Gates and Collector to Emitter voltage.
Gates of one of the IGBT modules (CM150DY-12H bricks):

(Measured the same waveforms on all Gates)

Testing at roughly Vbus = 70VDC:

Collector-Emitter voltage of one of the low side IGBTs (yellow), primary current (red)

(Measured the same waveforms on all transistors)

Bridge output at the start of interrupter pulse (yellow), primary current (red)


Bridge output at the end of interrupter pulse, close up (yellow), primary current (red)


It's been quite some time since I last scoped DRSSTC bridge, however isn't the bridge output looking kind of funny?
I have done these measurements at Vbus=70V and an iron pan as a load on the primary.

Not what I'd recommend, but you could patch the issue with a weak pull-down (~100k) on + input of comparitor, forcing idle state low.

This works as a charm! Thanks for the advice.. Before I test at higher power, may I know why do you not recommend this patch?

EDIT: I have noticed that tunning start-up oscillator frequency od the UD+ board helps a bit, but even if the start up frequency matches the resonant frequency exactly, some pulses are still getting skipped

[davekni]

I have measured whole bridge, all transistor's Gates and Collector to Emitter voltage.

All looks good.  If you want to scope the failure, I'd suggest adding a weak pull-up resistor to comparitor + input (instead of pull-down).  I suspect in the failed state one or more of the Vge signals will look wrong.

It's been quite some time since I last scoped DRSSTC bridge, however isn't the bridge output looking kind of funny?
I have done these measurements at Vbus=70V and an iron pan as a load on the primary.

The sine-wave part of H-bridge output is on Vbus (on 70V supply when scoped at H-bridge).  It is caused by resonance of local bridge snubber caps and interconnect (wiring or bus bars) from there to bulk caps.  Looks like your resonance is between 1x and 2x coil frequency, so likely not causing trouble.  A few people on this forum have had the misfortune of this resonance being at or very close to 2x coil frequency.  Most bus ripple current is at 2x coil frequency.  This resonance voltage can build to +-Vbus, so double peak Vbus at H-bridge.  If your primary frequency drops enough due to arc loading and/or tuning, you could possible hit this unfortunate 2x ratio.

This works as a charm! Thanks for the advice.. Before I test at higher power, may I know why do you not recommend this patch?

Patching an unknown issue always involves some risk.  The fault (cause of issue) may be stable.  If stable, patching is fine.  However, the issue might indicate other future issues.  A random example:  Suppose PLD programming was marginal and one bit has reverted states causing a logic change.  Patching works initially.  Eventually another marginally-charged internal PLD cell changes state.  This next failure might happen to be more catastrophic, destroying IGBTs or other circuitry.  (I don't recall experiencing this sort of PLD failure personally.  But I've used only three PLD part types over the past 30 years.)  Might be some other issue with UD+ board.  No way to know unless the failure is debugged and understood.

Good luck with either finding the issue or having it be stable so patching continues to work reliably.

BTW, you mentioned UD+ generating startup pulses.  If UD+ generates several (more than one) transition on gate signals before feedback starts, then no bleed resistor is needed across H-bridge outputs.  Of course, no harm in resistor other than a bit of wasted power.

[AstRii]

Good luck with either finding the issue or having it be stable so patching continues to work reliably.

Thanks Dave! Due to lack of time I'll unfortunately probably going to go with the latter. However I'm interested in the ratio of resonant frequencies primary:snubber-interconnect.
You mentioned 2x resonant frequency of parasitic inductance + snubber caps is problematic. I searched the forum for more info. Do I understand correctly that ratio of 2 is problematic because the voltage on Collector-Emitter can rise too high for the IGBTs to fail?
Is there some other problem as well with that?

Also it seems like you mention ratio = 2 but not ratio = 1. Wouldn't voltage climb even higher at ratio = 1?

[davekni]

Also it seems like you mention ratio = 2 but not ratio = 1. Wouldn't voltage climb even higher at ratio = 1?

As with most things, simulation is a great way to understand.  Vbus ripple current looks like a full-wave-rectified sine wave (for a full H-bridge).  Lowest frequency is 2x coil frequency, with harmonics of that.  There is very little 1x frequency component - only to the extent there is asymmetry in drive such as other than 50% duty cycle.

Do I understand correctly that ratio of 2 is problematic because the voltage on Collector-Emitter can rise too high for the IGBTs to fail?
Is there some other problem as well with that?

Only failure I'd expect is excess IGBT voltage.  Worst case is 2x Vbus.  IGBT diodes will clamp Vbus resonant voltage at Vbus +-Vbus (0 to 2x Vbus).

[AstRii]

As with most things, simulation is a great way to understand.

Well unfortunately, for me it makes me even more confused. Here I've tried to do an LTSpice simulation, with some realistic parasitic component values. The voltage I'm getting on the transistor don't make much sense to me.
I found the resonant frequency by stepping through multiple different frequencies until I found the highest primary current amplitude at around 125kHz, pretty close to my coil.

[davekni]

The voltage I'm getting on the transistor don't make much sense to me.

Try again with leaving off L1 and/or giving it a low-value parallel resistance.  Short interconnect inductance is important for inductive glitches.  But such short interconnect is also low-Q, especially at high frequency due to skin effect.  Hard to model accurately over wide frequency range.  For this specific investigation in the range of 50-200kHz, L1 is insignificant.  Easier left out.  The 500nH L2 has a much higher capacitance load, so a much lower frequency resonance.  Parallel loss resistance will also be significant, but much less so.

I found the resonant frequency by stepping through multiple different frequencies until I found the highest primary current amplitude at around 125kHz, pretty close to my coil.

Did you change C3 and/or L4 to match drive frequency?  That's the case you are interested in, driving at TC coil resonant frequency.  If C3//L4 is not tracking period variable, then of course you will get maximum issues at coil frequency.  At half frequency there is low primary current, so low ripple current on H-bridge Vbus supply.

[AstRii]

Try again with leaving off L1 and/or giving it a low-value parallel resistance.

Without L1 the high frequency ringing is gone. However the Drain voltage still looks odd.


This however gets rid of the inductance that I wish to simulate..
C2 current is also going in both polarities, something I would not expect.. I guess something is resonating? Perhaps C2 with L2?

Did you change C3 and/or L4 to match drive frequency?

I'm using fixed values for inductance of primary and MMC capacitance similar to what my coil uses.  I found resonant frequency of L4,C3 by stepping through different fres. The maximum current amplitude is between 125kHz - 135kHz.

[davekni]

Without L1 the high frequency ringing is gone. However the Drain voltage still looks odd.

I'd guess there is some issue with FET model, or else primary current is past FET current capability.  Drain voltage (left half-bridge output) is switching more often than Vgs (presuming Vgs is switching at 125kHz as it appears to).  BTW, if you want 50% duty cycle on Vgs, pulse on time needs to be period/2-200ns to account for rise time.

This however gets rid of the inductance that I wish to simulate.

As I mentioned, L1 is relevant for Vds switching spikes.  At that frequency you'll need parallel loss resistance.  Proper modeling at high spike frequency would require a more complex R/L network to simulate skin effect at a range of frequencies.  I rarely attempt such a complex model.  Just tweak parallel resistance to roughly match measured spike voltage.

I'm using fixed values for inductance of primary and MMC capacitance similar to what my coil uses.  I found resonant frequency of L4,C3 by stepping through different fres. The maximum current amplitude is between 125kHz - 135kHz.

To see the issue of snubber cap resonance at 2x frequency, you need to make primary resonate at 1x frequency.  Either change primary values or add secondary and arc loading model to change frequency.  Results are not meaningful for real DRSSTC drive which is at resonant frequency.

[AstRii]

I'd guess there is some issue with FET model, or else primary current is past FET current capability. 

You're right, I have used "M=10" command to use 10 of those in parallel. Now the Drain-Source waveform looks much more as expected.
With 15ohm parallel resistance on the inductor it seems quite similar to what I see in reality:


Do I understand that correctly that the parallel resistance is there to lower the Q of the inductor? How come R1 doesn't do that already? 1mOhm is quite high resistance for a copper bus bars, I doubt in reality it will be so high.

C2 current does not seem to be rectified sine wave, for some reason there is current flowing back to the capacitor as well. I thought this only happens at the end of "enable" pulse.

I have lowered the capacitance of C1 from 4.4uF (real coil) to 2.02uF to match 2x the resonance frequency of the primary circuit (125kHz). 2.02uF snubber with 200nF inductance gives roughly 250kHz.
Indeed the Drain-Source voltage reaches higher:


However it doesn't seem like the sinewave component on the Drain-Source voltage is 2x the frequency of the Drain-Source voltage.
Going even lower with the C1 capacitance seem to enlarge the sinewave component on the Drain-Source voltage:



However the sinewave component frequency doesn't seem to match the change in capacitance C1 from certain point (about <500nF)
For example here with 100nF, it seems like the frequency of the sinewave is actually lower:


Not really sure why all of this is happening.

[davekni]

Do I understand that correctly that the parallel resistance is there to lower the Q of the inductor? How come R1 doesn't do that already? 1mOhm is quite high resistance for a copper bus bars, I doubt in reality it will be so high.

Bus bar resistance is a function of frequency due to skin depth.  Simulators I'm familiar with don't have frequency-dependent resistor models, so R1 can't be modeled accurately by itself.  Current through R1 has frequency components from DC through MHz of spikes.  Parallel resistance is an imperfect fix for this frequency dependent Q.  For better understanding, calculate (or simulate) Q as a function of frequency for:
R+L (series)
R//L (parallel)
R+L with R proportional to sqrt(frequency).  Skin depth is proportional to 1/sqrt(frequency).  Bus bar geometry makes R1 not exactly proportional to sqrt(frequency), but close enough.

C2 current does not seem to be rectified sine wave, for some reason there is current flowing back to the capacitor as well.

It is the current of R1 (supply current to H-bridge) that should be a rectified sine wave.  That is true if primary (L4) current is a sine wave and H-bridge is switched at zero-current points of primary.

I have lowered the capacitance of C1 from 4.4uF (real coil) to 2.02uF to match 2x the resonance frequency of the primary circuit (125kHz). 2.02uF snubber with 200nF inductance gives roughly 250kHz.
Indeed the Drain-Source voltage reaches higher:

That is a good way to simulate 2x issue.  C1/L2 resonant frequency still isn't close enough to 250kHz to make the issue obvious.

However it doesn't seem like the sinewave component on the Drain-Source voltage is 2x the frequency of the Drain-Source voltage.

Looks like 2x to me.  Roughly one cycle in a half-cycle of Vds.

Going even lower with the C1 capacitance seem to enlarge the sinewave component on the Drain-Source voltage:

Not really sure why all of this is happening.

Calculate the value of C1 that makes 250kHz resonance with L2.  2.02uF is too high and 500nF is too low.

[AstRii]

That is a good way to simulate 2x issue.  C1/L2 resonant frequency still isn't close enough to 250kHz to make the issue obvious.

Ooh, I was under the impression that it's the C1/L1 which is causing this issue. Alright then if I tune C1 to 810nF which makes it around 250kHz together with 500nH of L2, the sinewave component reaches highest amplitude. In my simulation roughly 480V on the Drain, which is about 1.47x Vbus. ¨


However even if I match C1 to resonate with L1 at 2x the primary frequency, and increase parallel resistance of L2 from 1ohm to 2.5ohm to increase the Q, the effect is not exactly what I'm observing on my bridge. If we compare those side by side, mine seem to have different phase of primary current to the sinewave component current. Is that caused by not switching exactly at zero crossing in my real coil?



I'm also wondering.. the RMS voltage of such non square wave signal is most likely lower than if it was nice square wave. Does this affect the output power? Simulation says yes and quite drastically.

[davekni]

Your primary (L4 and C3) resonates at 130kHz.  Driving it at 125kHz makes simulation not switch at zero current.  With fixed frequency drive into a high Q load, small frequency changes make relatively large phase changes.  Probe primary current along with bridge voltage to see switching phase for your simulation.

Parallel resistance for interconnect inductance is tricky.  "Correct" value depends on inductance and frequency and a bit on physical geometry.  For 500nH at 250kHz, 2.5 ohms is likely low.  Probably 10-50ohms would be more realistic.

Yes, real power suffers when Vbus resonates at 2x coil frequency.  Average Vbus is constant, but Vbus is minimum when current is maximum.  Real power is lower.

Anders first three recommendations below are all good and ones I've used before.

[Anders Mikkelsen]

So your local decoupling is resonating with the wiring inductance between the local decoupling and the bulk capacitance. This is not ideal, and can be addressed in a few ways.

1: Reduce the stray inductance, this can make a huge difference. It should be possible to achieve a lot less than 500 nH. What does your layout look like at the moment?

2: Add RC snubbing across your local decoupling. 2.2 µF in series with 1 ohm takes the impedance peak at 200 kHz down from 100 ohms to around 1 ohm

3: Bulk up your local decoupling to move the resonance below the operating frequency. 47 uF would do it. This also lowers the resonant impedance to where the electrolytic ESR dampens it nicely.

3: Remove the local decoupling. This might help, but keep a close eye on the bus voltage if you try this.