Ramped DRSSTC

[alan sailer]

I was working on the tuning of a ramped coil using the labcoats circuit board. I was getting decent results but I had
purposefully wound the secondary coil below 300kHz. The result was more branched sparks.

Part way through this tuning process I turned up the PRF of the staccato interrupter to maximum ie highest pulse rate.
The circuit died with both IGBJTs dead.

I am puzzled as to the cause. I was monitoring the Vce of one device with a diff probe and the voltage spikes at low rep rate
were about 300 volts. The current through the primary was a bit over 50 amps. The IGBJTs are FGA60N65SMD and are rated
at a maximum Vce of 650V and IC of 120 amps.

I am kind of at a loss to decide what to look for when I get the unit up and running. The only thing I can think of is that the
interrupter is getting screwy at high rep rates.

The only other data I have that I can't fully explain is that I am using the output of the interrupter to trigger the scope. When
I look at that waveform it should be a simple 5 volt digital pulse but when I raise the power theer is a lot of noise on the signal
correlated to the operating frequency. I thought this was due to the fact that the 10x probe I am using has a large loop inductance
and should be picking up the secondary radiated energy. Could this be coupling back into the circuit and causing issues?

Red Vce Blue interrupter pulse

[Anders Mikkelsen]

Can you probe the primary current and capture it together with the bridge output voltage on the scope?

I'm not convinced by the use of antenna feedback together with a resonant primary in any Tesla coil. I'd be worried about losing soft switching in the primary, and given the use of IGBTs and 300-ish kHz switching frequency this would be a very bad thing indeed.

[Mike]

Power dissipation goes up approximately linearly with pulse repetition frequency (slightly worse in practice as hearing causes slower switching and higher loses). Are you sure you didn't just put too much power into the die? The IC rating of for a single 1ms pulse, it makes no guarantees about what happens with high frequency switching, especially during hard switching which is almost certainly occurring with secondary feedback as the secondary frequency is pulled further from the primary by steamer loading.

[alan sailer]

Two thought provoking replies.

Anders,

I can do this. By bridge output voltage do you mean the voltage across the primary tank or the Vce of one IGBJT.
Also, should I be zoomed in on a few cycles to check phasing? If so, at the start or finish?

Mike,

I was not aware of the spec being for a single pulse of 1msec. Is it a 1msec off-on-off pulse or a 1msec frequency burst?

Maybe I should bypass the antenna feedback and use primary feedback.

Cheers.

[Mike]

It's a single off-on-off pulse, however looking at the datasheet I can't find any mention of the 1ms, I may be misremembering, or it might have been specified that way for a different part.

Looking at the datasheet SOA graph it has lines for up to 10ms (and you could infer that it would be ok out to about 100ms), but with the usual notes that that is for a single pulse with Tc = 25°C which is very difficult to achieve in practice. When switching at hundreds of kHz, switching losses can be expected to be significant.

[alan sailer]

Mike,

In other words, read the manual dummy :-)

I admit to not looking at the data sheets all that carefully. I'd do a deeper dive tomorrow. Thanks much for the ideas.
I did replace the transistors today and the thing is making low PRF sparks.

Cheers.

[davekni]

It's a single off-on-off pulse, however looking at the datasheet I can't find any mention of the 1ms, I may be misremembering, or it might have been specified that way for a different part.

Many IGBT datasheets list 1ms as duration for specifying peak current.  Other datasheets just say duration limited by power dissipation.  Peak IGBT (and diode) currents are the only reference to 1ms I normally see.

Are you using an 8:12:12 ratio GDT?  Do you have any resistors across Vbus divider caps (caps connected to other side of primary) or across IGBTs to help initial voltage be center-supply?  Is there any capacitor across Vbus (from low-side emitter to high-side collector)?  Just looking to understand your build better to suggest possible causes for fried parts.

Do you know what duty cycle you were running at max PRF?  Are you confident that the interrupter never stops at high line voltage (middle of line half cycle)?

especially during hard switching which is almost certainly occurring with secondary feedback as the secondary frequency is pulled further from the primary by steamer loading

Hard switching can be either hard on-to-off (usually better) or hard off-to-on (usually more problematic, both for spikes and power dissipation).  Might be changing between those two as you change tuning and/or as arc builds.  I used to think SSTCs were almost always hard-switched on-to-off.  Appears to not be so universal.

Since this is listed as a DRSSTC, hard switching is likely changing modes (before to after current zero crossing for on-to-off to off-to-on).  Also difficult to predict what maximum primary current will be as tuning changes.  At resonance, arc loading is limiting primary current, not much else to limit current.

Random thoughts and questions.  Please feel free to answer whatever is convenient.

[Anders Mikkelsen]

Exactly, the voltage across the primary tank, so between the two outputs of the bridge, along with a sample of the current (which could be taken with for example a 30 turn CT into an ohm or so). The time scale should be fine enough to see the phasing between voltage and current, to see that there is ZVS and moderately close to ZCS throughout the whole burst.

Peak current and duration from the datasheet doesn't really apply here, as that's a single pulse thermal rating, i.e. what current for 1 ms will bring the die up to Tjmax starting from 25 C. In the presence of switching losses, this number no longer applies, and a pulse rating has to be extrapolated from transient thermal impedance and loss estimation, taking into account the rise of T_case from the average dissipation.

These calculations can be tedious and hard to do without knowing the actual waveforms and switching conditions, but as a point of reference we can compare conduction and switching losses in case soft-switching is completely lost. At 50 A, conduction losses at Tjmax would be around 90 W. If we assume 10 ms pulse length, transient thermal impedance is around 0.18 k/w, so the junction will rise around 16 degrees above the case temperature, this should be fine. Hard-switching losses are listed as 2.86 mJ at 60 A, Tj_max, and at 300 kHz this would represent 300e3 * 2.86e-3 = 860 W, bringing the junction 150 C above the case temperature for 10 ms pulse length. Real world conditions will likely be different depending on the actual currents and switching phase angle, but this should illustrate that switching losses with IGBTs are much more important than conduction losses, so any peak current figures from the datasheet become meaningless when soft switching is lost.

These are also frequencies where forward recovery in IGBTs can start to become dominant, so even having ZVS and ZCS, you can't assume that switching losses will be zero. But this is a minor effect compared to the regular switching losses.

For this circuit, I'd strongly consider changing the circuit to primary current feedback, as it's much simpler to guarantee soft-switching under real operating conditions with primary feedback. There's a reason antenna feedback was ditched with the introduction of primary resonance in SSTCs, and primary current feedback has been the standard solutions since early 2005 or so.

[alan sailer]

David,

Check on the GDT 8:12:12. No resistors yet. I gather they balance the initial charge on the voltage divider caps?

I'm confused about the extra capacitor across Vbus. Would it not tend to smooth the ramp effect? Or is the current
being drawn so large that this doesn't happen?

Attached are labcoatz schematic. That is the circuit board I'm using.



This is loneoceans Ramped SSTC schematic.



He is using a 680uF capacitor.

I am just getting started with the circuit so am not sure that the interrupter is working correctly at high rep rates. It's on the list.

Anders,

I did a quick look at the current and voltage waveform you suggested. My initial capture was so strange that I don't want to post it yet.
It looks more like a modern dance routine than a square wave. I'd like to make sure that it's real before I post.

Sorry.

And I intend to look into primary feedback. My only antenna based coil was a CW coil that worked just fine with antenna input but
other tried at it ended with switching to transformer feedback.

Cheers.

[ZakW]

Hello Alan,

Regarding Loneoceans ramped SSTC, he omits the 680uf cap in the ramped build. Take a look at the last couple of pictures of the final build and PCB. You can see it is not soldered on the PCB.

I included a 1uf film cap across the AC input in my build (sstc) to help reduce voltage spikes. It did add a slight snapping sound to the arc though.

[davekni]

No resistors yet. I gather they balance the initial charge on the voltage divider caps?

Yes, resistors balance charge.  Oscillation can fail to start if charge is too unbalanced.  I'm guessing that isn't your issue.

I included a 1uf film cap across the AC input in my build (sstc) to help reduce voltage spikes. It did add a slight snapping sound to the arc though.

Charge-balancing resistors can also reduce that initial snap by discharging caps between line half-cycles, if resistance is low enough to discharge in a reasonable time, which does add power dissipation.

Attached are labcoatz schematic. That is the circuit board I'm using.

That helps.  I was looking at the wrong schematic, one without "MMC".  Is MMC capacitance far below 0.68uF of voltage-splitting caps, ie. 80-100nF as on schematic?  If so, adding 1uF across rectified AC is not too important.  Adding at least a small capacitor or two there, perhaps 0.1 to 0.22 uF does help reduce parasitic inductance across supply, so help reduce IGBT Vce spike voltage.

I am just getting started with the circuit so am not sure that the interrupter is working correctly at high rep rates. It's on the list.

Difficult to read schematics like this that show pin numbers (or not even that like the 555 chips) rather than pin function labels.  However, I don't spot anything in the interrupter portion to force the end of interrupt pulses to be at line ~zero voltage.  Without bulk caps, end of interrupt enable at high line voltage (at high line current) causes a voltage spike due to inductance in incoming line wiring.  Line inductance is higher when using a variac or isolation transformer.  TVS diodes across IGBTs may be sufficient to absorb this line spike energy, but perhaps not if repeated frequently enough.  Probably best to tune interrupter on-time to be exactly half-line-cycle long.  BTW, did you include Vce TVS diodes?  If so, what parts?  This issue of line inductance is my best guess as to what fried your IGBTs.

And I intend to look into primary feedback. My only antenna based coil was a CW coil that worked just fine with antenna input but
other tried at it ended with switching to transformer feedback.

Secondary current feedback is another option.  Primary current feedback is especially risky without OCD.  If coil gets out of tune (due to arc load or tuning changes), primary current can increase until IGBTs fry.

[alan sailer]

It was good to post this question on the forum. It has forced me to go back and start looking more critically at the waveforms
of the circuit. When I do that I am getting such crazy images on my scope that I need to spend some time with it to figure out
what is happening.

Seriously, the question at this point is not why did it fail, but rather why did it work in the first place. I'm going to force operation
with a signal generator to eliminate the antenna feed back and go from there.

But it's not worth wasting anyone's time until I get a better handle on the circuit.