Author Topic: How does the Flip-Flop work using only the reset/clear pin?  (Read 726 times)

Offline RubyWindow

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I'm aware that the flip flop takes in both the interrupter output and feedback from the primary coil and only enables the gate drivers when the current in the primary is low. While looking at Loneocean's SSTC 3 https://www.loneoceans.com/labs/sstc3/schema_sstc3v1complete.jpg as well as the modified version by LabCoatz https://hackaday.io/project/182391/gallery#35e2b14d6393e248bf90c4be28b4658b I noticed that they both had the data and set pins set to high. So my questions are:

How is it that the reset pin by itself is able to change the values of Q and Q bar.
How is the feedback from the antenna going into the clock pin able to influence when the interrupter signals go through? I thought that the reset pins were asynchronous and wouldn't be influenced by the clock at all.

Sorry if this is just really obvious. I've spent hours watching videos and reading articles but it just doesn't seem to click.

Offline thaumatichthys

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Re: How does the Flip-Flop work using only the reset/clear pin?
« Reply #1 on: May 25, 2023, 06:31:45 AM »
I might be wrong but I think that it is asynchronous on the rising edge, but it only clocks the perpetually high data in signal to Q when the clock pin is triggered, thus only turning Q bar off synchronously.

This is because the flip flop is just to prevent the IGBTs from turning off when there is a lot of current running through them, and is not needed for when they turn on.

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Re: How does the Flip-Flop work using only the reset/clear pin?
« Reply #1 on: May 25, 2023, 06:31:45 AM »

 


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