Problem with SSTC

[davekni]

In any case, since I get the 90 VDC from a transformer, I shouldn't have any problems, right?

If you are probing both IGBT gates simultaneously, that is a serious problem.  The two emitters are shorted through scope probe ground connections.
If probing individually, not a huge problem, but high side Vge (gate to emitter voltage) may be distorted.  Scope "ground" is switching 90V suddenly.  Scope has significant capacitance to power lines even with "ground" disconnected.

[Nunu00]

If you are probing both IGBT gates simultaneously, that is a serious problem.  The two emitters are shorted through scope probe ground connections.
If probing individually, not a huge problem, but high side Vge (gate to emitter voltage) may be distorted.  Scope "ground" is switching 90V suddenly.  Scope has significant capacitance to power lines even with "ground" disconnected.

Yes, I was probing both igbt gates simultaneously 😅. So how should I probe the IGBTs correctly?

[davekni]

With no power to half-bridge, it is fine to probe both Vge's simultaneously, as you did before applying 90V.  Since those two Vge waveforms look good and symmetric, there isn't any real need to probe high-side Vge after Vbus is applied.  Most useful to simultaneously probe low side IGBT Vge and low side IGBT Vce (half-bridge output).

Of course, the expensive option is to purchase a differential probe for your scope.

[Nunu00]

I redid some tests following the instructions.

With the 90 VDC applied the waveform in the gate looks like this:



These instead, are the waveforms between collector and emitter:







These are the Vge vs the Vce:





And finally this is a photo of the discharges:

[davekni]

Generally looks good.  A few details to consider:

Dead time may be too small.  6R8 gate resistors (R1 and R3) are low value for FGA60N65 IGBTs.  I'd guess 30 ohms would be more appropriate.

Vce spikes might be OK, but need checking as Vbus is increased towards 350V.  Need to be well below 600V peak.

Schematic doesn't show any capacitors across Vbus (across 350V supply).  Theoretically not necessary, but added capacitors reduces stray half-bridge inductance so will reduce Vce spikes.  Good half-bridge layout helps too, such as:
    https://highvoltageforum.net/index.php?topic=1324.msg9795#msg9795

[Nunu00]

Schematic doesn't show any capacitors across Vbus (across 350V supply).  Theoretically not necessary, but added capacitors reduces stray half-bridge inductance so will reduce Vce spikes.  Good half-bridge layout helps too, such as:

The capacitors were already present on another board. Anyway I followed the advice and redid the layout of the half bridge as you can see from the photos:

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The changes seem to have worked, in fact now the Vce does not show any obvious spikes.

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Dead time may be too small.  6R8 gate resistors (R1 and R3) are low value for FGA60N65 IGBTs.  I'd guess 30 ohms would be more appropriate.

I didn't have 30 ohm resistors so I used 15 ohm ones. From what I see the dead time seems to have increased but the Vgs shape seems to have worsened. Is it really like that?

[davekni]

Anyway I followed the advice and redid the layout of the half bridge as you can see from the photos:

One detail I'd suggest following more accurately:  Emitter side of GDT secondary leads should connect as close as possible to IGBT emitter leads.  At least to copper foil where emitter is soldered if not directly to emitter lead adjacent IGBT body.  Definitely not to bulk cap terminal as is now for low side emitter.

The changes seem to have worked, in fact now the Vce does not show any obvious spikes.

Great.  That's exactly what low inductance half-bridge layout is intended to fix.

I didn't have 30 ohm resistors so I used 15 ohm ones. From what I see the dead time seems to have increased but the Vgs shape seems to have worsened.

Presume you are referring to Vge since using IGBTs.  Looks reasonable, though may improve a bit once GDT emitter wires are attached closer to IGBT emitter leads near IGBT body.  Rising edge spikes are due to Miller capacitance (Cgc).  Can be avoided only if achieving phase-lead where Vce transitions due to remaining collector current prior to opposite IGBT turning on.  Phase lead isn't always possible with SSTC designs.
Dead time might be sufficient.  Difficult to measure without phase lead.

[Nunu00]

One detail I'd suggest following more accurately:  Emitter side of GDT secondary leads should connect as close as possible to IGBT emitter leads.  At least to copper foil where emitter is soldered if not directly to emitter lead adjacent IGBT body.  Definitely not to bulk cap terminal as is now for low side emitter.

I made this last change and the Vge improved slightly.

Then I finally connected it to the rectified  230 mains and everything worked fine. I also made an interrupter with an arduino that reads midi files from a micro sd and it works really well.

https://youtube.com/shorts/lrdIRCy-Lns

The only problem is that I probably have to add an emi filter on the power supply because the house differential switch (GFCI) trips. Any tips on how to make one?

[davekni]

I made this last change and the Vge improved slightly.

Good.  Will make more difference when running at high power.

Then I finally connected it to the rectified  230 mains and everything worked fine. I also made an interrupter with an arduino that reads midi files from a micro sd and it works really well.

Great!  Thank you for sharing good news.

The only problem is that I probably have to add an emi filter on the power supply because the house differential switch (GFCI) trips. Any tips on how to make one?

Likely most important part is good common-mode choke(s) in series with line input.  One good choke is likely sufficient.  Sometimes two in series can help further, one large for low frequencies and a smaller one (with less inter-winding capacitance) for higher frequencies.