First SSTC based on profdc9 PCB Pack

[SK1701]

Hey guys.

After years of wanting to build an SSTC, I've started work on my first build. I am using the schematics kindly provided by profdc9 (https://github.com/profdc9/DRSSTC-PCB-Pack) for the driver and full bridge (with FGH60N60SMD). I had the PCBs fabricated at JLCPCB and I have started assembling them now. I thought I would make this thread to ask questions as well as document my progress. I had a couple questions to start off with:

• This driver doesn't seem to have any sort of interrupter built in. Does this mean the coil will be operating in CW mode the whole time and so won't heat/ power be a concern?
• I typically see ~30 AWG wire used for the secondary. The most readily available source here is 1/2 lb spools of 29 AWG. Would this still work, i was planning a secondary diameter of ~4 inche PVC pipe?
• I am using the following bus capacitor - https://lcsc.com/product-detail/Aluminum-Electrolytic-Capacitors-Can-Screw-Terminals_Zeasset-TAG102M51080LVA_C432125.html with aa 100k 20 W bleeder resistor. How much of a concern is inrush current, and could you recommend appropriate NTC thermistors for current limiting? Would using a variac remove the need for inrush limiting?

Cheers!

[alan sailer]

SK,

The profdc9 github package also has two boards for two types of interrupter normal and line interrupter. It couples to the UD board using optical fiber.

JavaTC will give the total wire length your proposed secondary will need. If the 1/2 lb spool has that amount of wire you are good. The wire length depends on
both the diameter and the length of the secondary.

The inrush current is a concern. I am not directly familiar with the NTC as an inrush current limiter. A Variac (and the discipline to always turn the Variac to zero after each run!)
will eliminate the need for inrush limiting. The capacitors will charge much faster than any rotation of the variac dial.

Cheers.

[SK1701]

Thanks Alan!

I assumed his interrupter designs were for the UD board. This driver isn't the UD (which as I understood is for DRSSTCs). It is the regular SSTC driver posted here - https://github.com/profdc9/DRSSTC-PCB-Pack/tree/master/half-bridge-sstc There is no fiber optic input for an interrupter and the enable pins of the gate driver chips are left floating

[alan sailer]

Sorry about overlooking the SSTC/DRSSTC distinction.

I have not built an SSTC like the design shown so I can't help. Hopefully a better experienced builder will help.

Cheers.

[davekni]

This driver doesn't seem to have any sort of interrupter built in. Does this mean the coil will be operating in CW mode the whole time and so won't heat/ power be a concern?

The schematic you posted does include an optical isolator, disabling operation when the isolator LED is energized.  You could use that for interruption.  I don't see any other interrupter functionality.  Continuous operation can be fine.  That is the way my SSTC runs.  Behavior is somewhat different relative to interrupted operation.
https://highvoltageforum.net/index.php?topic=1021.msg7119#msg7119

How much of a concern is inrush current, and could you recommend appropriate NTC thermistors for current limiting? Would using a variac remove the need for inrush limiting?

Either works.  Two NTC specification parameters are most important:  First is energy capability.  NTC must be rated to handle the energy stored in your bulk capacitor.  Look for units of Joules.  Second is continuous current (RMS amps).  Necessary rating depends on the power your coil will draw during operation.  Somewhat less important specification is cold (nominal) resistance.  That determines what the initial inrush current will be.  Building power circuits are designed to handle inrush of incandescent light bulbs and motors, often 10x rated continuous current.  Finally, most NTC inrush limiting designs use a relay to bypass (short across) the NTC a few seconds after power-up.  For home projects I often skip this, but NTC reliability isn't great when used continuously near rated current.

[SK1701]

I had the chance to test the output of my driver board and this is what I got feeding a 250 kHz sine wave to the feedback antenna. How does the GDT output look in terms of ringing and dead time? There seems to be more ringing than I was expecting so do i need to make any changes? The last thing I have left to do on this build is winding the secondary.

[davekni]

I had the chance to test the output of my driver board and this is what I got feeding a 250 kHz sine wave to the feedback antenna. How does the GDT output look in terms of ringing and dead time? There seems to be more ringing than I was expecting so do i need to make any changes? The last thing I have left to do on this build is winding the secondary.

I'm guessing this is unloaded GDT output (not connected to H-bridge).  Unloaded GDT testing is useful for verifying minimum operating frequency capability of the GDT.  Leakage inductance issues don't show up without load (gates).  The bridge can be left unpowered, just connected to GDT outputs.  (Vge waveforms will change some with bridge power, but that's not critical for initial GDT testing.)

Ring frequency (~8MHz in your plots) does seem a bit low for an unloaded GDT, though could be reasonable if scope cable is long or whatever.  BTW, here's my little GDT construction tutorial in case it helps:
https://highvoltageforum.net/index.php?topic=1854.msg13949#msg13949

If you have pictures of your driver, GDT, bridge, and bulk caps, showing how they are interconnected, that may help.  Excess parasitic inductance is sometimes obvious from images of construction.

[SK1701]

Thanks for the help! I finished assembling the bridge and scoped the GDT waveform from gate to emitter. Seems to look slightly overdamped but not too bad (though I would appreciate any suggestions). All thats left to do now is get my hands on a variac so I can test.

I also had a couple of questions regarding the primary. Is there a way to know what the correct phasing is based on the direction of the windings or is it just found through trial and error? What are some good materials/ ways to separate the primary and secondary to avoid flashover?

[davekni]

Seems to look slightly overdamped but not too bad (though I would appreciate any suggestions).

Yes, a bit over-damped, but should be fine.  If you want to reduce damping, I'd suggest reducing the value of driver R10, from 3.3ohms to something less.  You could parallel another 3.3ohm resistor for 1.65ohms.  Or even try shorting R10 to 0ohms.

Is there a way to know what the correct phasing is based on the direction of the windings or is it just found through trial and error?

Yes, phasing can be calculated.  I don't know of anyone who has bothered with that.  There are enough steps through the circuit that it is easy to miss one inversion.  It is easier to test, at low power of course.

What are some good materials/ ways to separate the primary and secondary to avoid flashover?

Flash-over is more common with DRSSTCs than with SSTCs.  Reducing flash-over risk is as much art as science, sometimes counterintuitive.  For example, sometimes thicker insulation can be worse.  If it leaves a very tiny gap between insulation and secondary, corona can form there, leading to a conductive air path around insulation.  If sealed against secondary, this isn't an issue.  Some people have used just many wraps of electrical tape around secondary, then wound primary on top of that.  More common is a plastic pipe with inside diameter a bit larger than secondary outside diameter.
Hopefully you will get other opinions here.  Search the forum for examples.  Polypropylene or polyethylene are ideal materials, but hard to find as tubing.  PVC is much more common.

[Mads Barnkob]

Seems to look slightly overdamped but not too bad (though I would appreciate any suggestions).

Yes, a bit over-damped, but should be fine.  If you want to reduce damping, I'd suggest reducing the value of driver R10, from 3.3ohms to something less.  You could parallel another 3.3ohm resistor for 1.65ohms.  Or even try shorting R10 to 0ohms.

3R3 is already a fairly low gate resistance for 250 kHz, but if your MOSFETs has a built in gate resistor, it could properly just be by-passed as Dave suggests. If a lower gate resistor does not help, you need a more powerful driver or lower the frequency.

Is there a way to know what the correct phasing is based on the direction of the windings or is it just found through trial and error?

Yes, phasing can be calculated.  I don't know of anyone who has bothered with that.  There are enough steps through the circuit that it is easy to miss one inversion.  It is easier to test, at low power of course.

I bothered to visualize it on my DRSSTC drivers, as inverted signals can be quite fatal there For SSTC I just increasing voltage from variac and if there is only a small breakout at 100V, I flip the polarity of the primary coil, simply because its the easiest to reverse polarity on, in my own builds.

What are some good materials/ ways to separate the primary and secondary to avoid flashover?

Flash-over is more common with DRSSTCs than with SSTCs.  Reducing flash-over risk is as much art as science, sometimes counterintuitive.  For example, sometimes thicker insulation can be worse.  If it leaves a very tiny gap between insulation and secondary, corona can form there, leading to a conductive air path around insulation.  If sealed against secondary, this isn't an issue.  Some people have used just many wraps of electrical tape around secondary, then wound primary on top of that.  More common is a plastic pipe with inside diameter a bit larger than secondary outside diameter.
Hopefully you will get other opinions here.  Search the forum for examples.  Polypropylene or polyethylene are ideal materials, but hard to find as tubing.  PVC is much more common.

I like as high coupling as possible for SSTCs, mainly because low coupling always gave me bad results. I used electrical tape and plastic sheets from inside LCD monitors, 4-5 layers of those. Before that I had flash-over between a single sheet of plastic from secondary to primary coil. Upper vinding. You can see it fail here, that it starts small (reflection in topload in the left side) and grows bigger and bigger, so it was melting.

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Taking care about frequency properties of the materials used is the most important, to avoid failures from melting plastics due to RF heating. I have some good materials listed in the secondary coil construction part of the DRSSTC design guide: http://kaizerpowerelectronics.dk/tesla-coils/drsstc-design-guide/secondary-coil/

[davekni]

3R3 is already a fairly low gate resistance for 250 kHz, but if your MOSFETs has a built in gate resistor, it could properly just be by-passed as Dave suggests. If a lower gate resistor does not help, you need a more powerful driver or lower the frequency.

As a clarification, this 3R3 resistor is on the driver board, in series with GDT primary.  It is thus equivalent to 13.2 ohms per IGBT gate.  There is an additional 10ohms paralleled with a diode on each gate.  So, as it exists, it is behaving as 13.2 ohms turn-off and 23.2 ohms turn-on per gate.  That (along with demonstrated undershoot) is why I suggested lower resistance.  It is the same as Mads suggestion of a stronger driver.  Lowering this resistor is making the driver stronger.
BTW, some level of undershoot on falling edges is expected and does no harm.  Given the higher gate resistance for rising edges (necessary to provide dead-time), proper rising-edge damping will cause some under-damping of falling edges.

[Mads Barnkob]

3R3 is already a fairly low gate resistance for 250 kHz, but if your MOSFETs has a built in gate resistor, it could properly just be by-passed as Dave suggests. If a lower gate resistor does not help, you need a more powerful driver or lower the frequency.

As a clarification, this 3R3 resistor is on the driver board, in series with GDT primary.  It is thus equivalent to 13.2 ohms per IGBT gate.  There is an additional 10ohms paralleled with a diode on each gate.  So, as it exists, it is behaving as 13.2 ohms turn-off and 23.2 ohms turn-on per gate.  That (along with demonstrated undershoot) is why I suggested lower resistance.  It is the same as Mads suggestion of a stronger driver.  Lowering this resistor is making the driver stronger.
BTW, some level of undershoot on falling edges is expected and does no harm.  Given the higher gate resistance for rising edges (necessary to provide dead-time), proper rising-edge damping will cause some under-damping of falling edges.

I did not look at the schematic, as I thought you also talked about 3R3 gate resistors directly at the MOSFETs.

I would lower the 10R to 6R8/4R7 before touching the GDT primary resistor, in order to protect the MOSFET driver IC outputs.

[davekni]

I would lower the 10R to 6R8/4R7 before touching the GDT primary resistor, in order to protect the MOSFET driver IC outputs.

Great point about driver IC power dissipation!  I'd forgotten to calculate that.  I think this is being ran uninterrupted.  Driver power dissipation could be problematic even with 3R3 ohms, and would be worse with lower resistance.  I'd check driver IC temperature during one of your signal-generator tests before powering the IGBT H-bridge.

Reducing the 10R gate resistors will add a bit to driver power, so even that could be an issue.  Also, reducing the 10R gate resistors will reduce dead-time.  You probable have sufficient dead-time margin for these relatively-fast IGBTs, so that reduction is not likely a problem.