Output stage of Steve Wards 1.3b driver

[Jesperb123]

Hi everyone!

I've been trying my best to understand the schematic for Steve Wards 1.3b driver, but i'm having a hard time understanding the output stage to the GDT. I've used LTspice with some some similar mosfets (they're rated for Vds of -60V and 60V and have a similar gate charge - I couldn't find the L/W/Kp/lambda for the actual mosfets).



These are my conclusions so far (please tell me if i'm wrong):
The additional mosfets connected externally to the UCC2743 are used to switch a higher output voltage than what the UCC can provide. There are two push/pull pairs that work together so we can send current both ways through the GDT - which creates alternating voltages on the GDT secondaries.

I simulated the top pair with this schematic:


Here are the traces:


From this I've gathered that C1 and R2 are used to generated the pulse (the top most trace). The green trace is the voltage source that goes from 9V to 0V after 1ms. Initally the voltage at the node n1 is 24V (when the supply is high) since no current flows through the cap/resistor, but when the supply goes low the voltage at this node drops since the C1 begins charging through R1 (and R1s voltage drop brings down V(n1)). M2 briefly starts to conduct when n1 goes below some thresholdvoltage, and stops conducting when C1's charge is high enough to pull the n1 voltage above M2s threshold voltage. This genereates the positive pulse (while the other part of the circuit generates the negative pulse). Here comes a million questions

What purpose does the diode have? is it to limit the voltage at n1 to less than 24+a diode drop?
Another thing I don't understand is the capacitors in the output path (C3 and C2). They seem to increase the fall time of the purple output trace (compared to running the simulation without them). Do I need to choose values for these?

Also, Steve's schematic show mosfets with body diodes across the drain and the source of the mosfets. I presume these are important when we are driving an inductive load but the suggested mosfets (STB16NF06 Nfet and SPB18P06 G Pfet) doesn't seem to have these. Is this some intrinsic property of all mosfets? What am I missing?

Last question: Why does the UCC state that it can provide 4A of output current, but it doesn't mention the output voltage at which it can do this?

Best regards
Jesper Bolin

[johnf]

you have surmised correctly what the diode is for.
C2, C3 are to capacitively couple the GDT to avoid core walk hence saturation due to DC offset they are sufficiently high in value to make sure that no resonances are present near the operating frequency, R11 is a "Q" killer for the same reason acting as a snubber to quench ringing

[davekni]

Your simulation grounds the bottom of C2/C3/R1.  That is modelling a shorted GDT.

[Jesperb123]

Your simulation grounds the bottom of C2/C3/R1.  That is modelling a shorted GDT.

I tried using inductances to model the GDT but I didn't get it to work so I just grounded the node. I will have to try it again.

you have surmised correctly what the diode is for.
C2, C3 are to capacitively couple the GDT to avoid core walk hence saturation due to DC offset they are sufficiently high in value to make sure that no resonances are present near the operating frequency, R11 is a "Q" killer for the same reason acting as a snubber to quench ringing

That seems complicated but now I know what to google atleast. Thanks alot!

[Hydron]

I'll see if I can dig up my model of a GDT + connections - I measured then modelled what I'm using for a QCW a while back (it will be significantly lower inductance than most DRSSTC GDT setups, but may be a useful starting point).

[Jesperb123]

Hi Hydron!
I'm sure that would help alot considering i'm starting from scratch