Comments and questions on Staccato controller circuit

[Sando3450]

Hello, first post here.

As an initial step towards attempting my first VTTC, I built the "staccato" controller following the details of the one on Mads' / Kaizer website. (Very grateful that the circuit schematic and stripboard layout were still available thankyou Mads!)

https://kaizerpowerelectronics.dk/tesla-coils/kaizer-vttc-i/

I know I'm about 20 years late to this party and there are nice kits available these days, but I had all the old stuff lying around to build it.

I am interested to find out from others who have built this or a similar circuit such as on Steve Ward's website how it went?



In my case I had some problems and had to change some component values to get this circuit working in the way I "think" it's supposed to work. I am wondering if others have replicated this circuit and whether my issues were well known or perhaps due to my use of ancient and scrounged parts, or me misunderstanding the design?



With reference to the schematic on the Kaizer website, here were my changes to make it work:
C4 changed from 100nF to 10nF because it was holding trigger pin of IC2 low for too long compared with the RC delay (if the pulse length was set to be short) causing IC2 to have undefined output at certain settings
C6 changed from 200nF to 470nF so I could get the maximum pulse length for the single pulse to be as long as the AC half cycle when the potentiometer R8 is set to maximum (max pulse length was only a quarter of the AC cycle till I changed this)
C7 changed from 1nF to 10nF because the trigger pulse to pin 2 of IC 3 through this cap was so small it was not triggering the IC 3 consistently.
Have others had to make these kinds of changes?

Also a comment - in my pic you can see the giant Lego bricks capacitors used for C9. This could have been a 10 microFarad electrolytic about 1/20th the physical size but the lego bricks I had gave me slightly less RC delay/interrupt at minimums with my 50k pot so I could potentially get the staccato output pulsing on every half wave with the interrupt set to the minimum.

Final question is probably a dumb one but what is the reason for having the transistor Q2? The overall result of this is the staccato circuit output goes high when the AC half wave going to the staccato controller circuit is negative. This just seemed confusing to me; if the IC 2 is triggered from Q1 instead, the staccato circuit output goes high when the AC half wave is positive. Isn't that more desirable / intuitive? I actually pulled Q2 and R19 off and linked the collector of Q1 directly to C4 instead but maybe this is a mistake. Q2 wouldn't be there in this design for no reason... Can anyone educate me?

Thanks, John.

[ZakW]

Hello Sando,

I do not have any experience with VTTCs, however, I have used a modified version of that circuit in my Ramped SSTC. My schematic can be found here https://highvoltageforum.net/index.php?topic=2338.msg20174#msg20174.

For what it's worth I did try getting the ZCD to work with an optocoupler, Arduino, and small AC transformer. The opto and Arduino worked okay, the AC transformer was solid, but I ended up using one of these small signal transformers in my final design https://www.amazon.com/gp/product/B07FTJCFQX/ref=ppx_yo_dt_b_search_asin_title?ie=UTF8&psc=1.

C4 changed from 100nF to 10nF because it was holding trigger pin of IC2 low for too long compared with the RC delay (if the pulse length was set to be short) causing IC2 to have undefined output at certain settings
C6 changed from 200nF to 470nF so I could get the maximum pulse length for the single pulse to be as long as the AC half cycle when the potentiometer R8 is set to maximum (max pulse length was only a quarter of the AC cycle till I changed this)
C7 changed from 1nF to 10nF because the trigger pulse to pin 2 of IC 3 through this cap was so small it was not triggering the IC 3 consistently.

My initial design was based on a modified version of this circuit from a YouTuber I follow. After building it and simulating it I found I had to make most of the changes you described. Mine were a bit different though - I increased C4 to 200nf, many values worked but if I went too small I would get inconsistent operation. I changed C6 to 560nF so that I could adjust well past 1/4 cycle. Allowing the voltage to ramp down to zero again made for the most quiet arcs. Lastly, I also had to increase C7 as the original value was too small and did not work.

Also a comment - in my pic you can see the giant Lego bricks capacitors used for C9. This could have been a 10 microFarad electrolytic about 1/20th the physical size but the lego bricks I had gave me slightly less RC delay/interrupt at minimums with my 50k pot so I could potentially get the staccato output pulsing on every half wave with the interrupt set to the minimum.

I used a 10uF ceramic cap without issues.

Final question is probably a dumb one but what is the reason for having the transistor Q2? The overall result of this is the staccato circuit output goes high when the AC half wave going to the staccato controller circuit is negative. This just seemed confusing to me; if the IC 2 is triggered from Q1 instead, the staccato circuit output goes high when the AC half wave is positive. Isn't that more desirable / intuitive? I actually pulled Q2 and R19 off and linked the collector of Q1 directly to C4 instead but maybe this is a mistake. Q2 wouldn't be there in this design for no reason... Can anyone educate me?

I wish I knew, I am curious now as well. I am trying to go back and improve my understanding of circuits more so hopefully someone can answer. In the meantime this might help - here is a simulation of my circuit using falstad https://tinyurl.com/4bb8ccyk alternatively you can download the text file and then open it in falstad to load the simulation.

[davekni]

    Final question is probably a dumb one but what is the reason for having the transistor Q2? The overall result of this is the staccato circuit output goes high when the AC half wave going to the staccato controller circuit is negative. This just seemed confusing to me; if the IC 2 is triggered from Q1 instead, the staccato circuit output goes high when the AC half wave is positive. Isn't that more desirable / intuitive? I actually pulled Q2 and R19 off and linked the collector of Q1 directly to C4 instead but maybe this is a mistake. Q2 wouldn't be there in this design for no reason... Can anyone educate me?


I wish I knew, I am curious now as well. I am trying to go back and improve my understanding of circuits more so hopefully someone can answer. In the meantime this might help - here is a simulation of my circuit using falstad https://tinyurl.com/4bb8ccyk alternatively you can download the text file and then open it in falstad to load the simulation.

Given Vbe of Q1 and Vf of D2, Q1 switches state when line voltage is slightly above zero.  With Q2 removed, output pulse is on positive half-line-cycle, but slightly after zero crossing.  With Q2, output is on negative half-cycle, slightly before zero crossing.  I'm guessing that slightly before zero crossing produces better TC performance in at least some cases.

[Sando3450]

Thankyou to both ZakW and davekni for these excellent and helpful replies!

ZakW - nice to know you made some similar alterations like I did - and noting some of your changes and observations might well be relevant to me once I am actually in a position to use this on the VTTC. Thanks for the link to the very comprehensive schematics on your Ramped STTC too - great documentation.

davekni - thankyou yes you are absolutely correct - this was a subtlety I did not pick up on my scope trace but I have now verified it with Q2 reinstalled looking closely at the timings. That makes perfect sense as to why the circuit was designed the way it was.

Thanks guys!

[ZakW]

You're welcome, glad I could help a bit. Looking forwarding to seeing your build!

-Zak