Author Topic: PLL "IHFSSTC" concept and schematic  (Read 3316 times)

Offline Lucasww

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PLL "IHFSSTC" concept and schematic
« on: January 19, 2024, 09:01:31 AM »
So, I want to try recreating the interrupted / QCW HFSSTC which i've seen from Jmartis2 and Steve Ward respectively. It seems like the best way to do this is with a PLL, so i've designed a driver circuit and before I try to build anything, I wanted if anyone here has input.

First thing to note here, using the "proper" class E circuit is difficult if the coil is going to be interrupted at a high BPS, because the large current through the RF choke will force the voltage on the MOSFET drain very high after an interrupter pulse ends.
You can see the problem here, the blue trace shows drain voltage and the green shows RFC current when the gate drive signal suddenly stops.


So it's far easier to use the simplified class E circuit that's used commonly in small coils, but not as much in HFSSTCs.
The circuits i'm referring to, for clarity:


The main drawback of this that i'm aware of is that the primary current is limited by it's impedance, whereas in a proper class E coil a series resonant capacitor can be used to cancel out the impedance of the primary, and thus greatly increase the primary current. To compensate, very few turns are typically used in the simplified version. I will try to use one turn.

Another thing of note here, when using this simplified class E circuit, the secondary current at resonance will be roughly in phase with the gate drive voltage (at least, according to my simulations). SSTCs typically use current feedback, so this means the PLL would have to be set to maintain a zero degree phase shift. This is perfect for using phase comparator 2 in the HC4046, but i've heard PC2 can be a bit unstable when driving SSTCs (tendency to get stuck at the lower or upper frequency, and other issues), so I tried to come up with a good way of using PC1. Heres the schematic I settled on after some simulation.



We take current feedback from the secondary coil, but shunt the CT with a capacitor. This adds an almost 90 degree phase delay to the feedback voltage, so it is in phase with the secondary voltage. the propagation delay in IC7 will roughly make up for the remaining delay to get to 90 degrees. Now, we use PC1 to maintain a 90 degree phase shift between the feedback signal and the gate drive voltage. VCO output is sampled from after the gate drive stage to avoid issues with the gate driver's propagation delay. As with my fixed frequency coil, capacitors give a slight negative voltage bias to the gate drive signal so that the FET is driven at around -3v to 15v. C26 reduces power dissipation in R9. R15 and D5 force the PLL to start above resonance.

I think that's about it. Any feedback is greatly appreciated, as I don't have that much experience with PLL.
« Last Edit: January 19, 2024, 09:34:46 AM by Lucasww »

Offline davekni

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Re: PLL "IHFSSTC" concept and schematic
« Reply #1 on: January 19, 2024, 07:48:09 PM »
Quote
First thing to note here, using the "proper" class E circuit is difficult if the coil is going to be interrupted at a high BPS, because the large current through the RF choke will force the voltage on the MOSFET drain very high after an interrupter pulse ends.
I'd thought the same.  However, for a high frequency coil, the choke inductance can be reasonably low.  Calculate stored energy.  For my 13.56MHz HFSSTC, choke energy is ~500uJ.  I haven't tried interrupting it.  However, if I were to try, a simple Vds clamp should be sufficient.  Even at 2kHz interruption frequency, clamp power is only 500uJ * 2kHz = 1W.
Of course, the "simple" version has even less stored energy, so less wasted power due to interrupting.
David Knierim

Offline Lucasww

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Re: PLL "IHFSSTC" concept and schematic
« Reply #2 on: January 21, 2024, 08:40:25 AM »
Yes, I realize the inductance can be very low. I may switch back to the proper class E circuit if I have issues with the simplified version. I plan to interrupt it at fairly high frequencies if I can so i'd like to keep it this way for now. I believe everything should work, so I designed a circuit board and will get it manufactured soon if I don't find any issues with this circuit.

If anybody with more PLL experience than me could take a look at the schematic and make sure there's nothing obviously wrong, it would be appreciated ;)
 



One other thing, what would be a good core material for a current transformer at 8+ MHz? I'm thinking some NiZn ferrite but i'm not sure.
« Last Edit: January 21, 2024, 09:13:14 AM by Lucasww »

Offline davekni

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Re: PLL "IHFSSTC" concept and schematic
« Reply #3 on: January 21, 2024, 10:08:00 PM »
Only one non-critical detail comes to mind:  D6 and D7 are not very effective since there forward voltage drop will be similar to that of IC7's internal diodes.  Generally best to either use schottky diodes (ie. BAT54) or to add a small resistor in series with IC7 input.  However, IC7 may handle input current without functional issues, especially since it is a single gate without adjacent circuitry to be bothered by substrate current.

Quote
One other thing, what would be a good core material for a current transformer at 8+ MHz? I'm thinking some NiZn ferrite but i'm not sure.
Yes, NiZn ferrite is the best option AFAIK.  That's what I use on my 13.56MHz HFSSTC for GDT core.
David Knierim

Offline Lucasww

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Re: PLL "IHFSSTC" concept and schematic
« Reply #4 on: January 22, 2024, 03:37:56 AM »
Quote
Only one non-critical detail comes to mind:  D6 and D7 are not very effective since there forward voltage drop will be similar to that of IC7's internal diodes.  Generally best to either use schottky diodes (ie. BAT54) or to add a small resistor in series with IC7 input.  However, IC7 may handle input current without functional issues, especially since it is a single gate without adjacent circuitry to be bothered by substrate current.

I think it should be fine as-is, but I'll add a 47 ohm resistor in series like this.


How does this core look? the datasheet specifies it up to 300MHz. https://www.mouser.com/ProductDetail/KEMET/ESD-R-16C?qs=BenOyfdfAroSLEUhkU6TIw%3D%3D

Offline davekni

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Re: PLL "IHFSSTC" concept and schematic
« Reply #5 on: January 22, 2024, 05:19:22 AM »
Quote
How does this core look? the datasheet specifies it up to 300MHz. https://www.mouser.com/ProductDetail/KEMET/ESD-R-16C?qs=BenOyfdfAroSLEUhkU6TIw%3D%3D
Looks like a good part.  Very similar characteristics to the one I used for a GDT, CST16/7.9/14-4S2 from Ferroxcube:
    https://www.ferroxcube.com/upload/media/product/file/Pr_ds/cablesh.pdf
Since inductance/turn^2 and/or permeability aren't usually specified for NiZn cores (too non-linear), high impedance at operating frequency is best gauge of suitability.  I haven't personally tried current transformers above 500kHz, so can't say anything definitive for CT use.

BTW, if you are in USA, I can send you a few CST16/7.9/14-4S2 cores.  I have plenty left over from my failed DRSSTC dynamic primary tuning experiment.
David Knierim

Offline Lucasww

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Re: PLL "IHFSSTC" concept and schematic
« Reply #6 on: January 22, 2024, 05:36:20 AM »
Heres the impedance curve from the datasheet.

It looks to me like it should be happy at 8MHz.

Quote
BTW, if you are in USA, I can send you a few CST16/7.9/14-4S2 cores.  I have plenty left over from my failed DRSSTC dynamic primary tuning experiment.
I'm in California, definitely interested if it's possible.

Offline Lucasww

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Re: PLL "IHFSSTC" concept and schematic
« Reply #7 on: February 04, 2024, 08:45:53 AM »
Got this put together a few days ago and it ended up pretty much working right away. I had some issues with the VCO getting stuck above it's frequency range, and I couldn't figure out why so I just added some diodes to make sure the VCO voltage is clamped from around 0-4V. this seemed to solve the issue without effecting anything else.

Here's the schematic as-built, and it's currently running happily from 15-60VDC input.
(I used the R5000F diodes since I have a bunch of them from another project. A 4V zener would probably work fine but I don't have one on hand)

And the board


Current transformer feedback works great. Secondary base feedback seems to also work alright but I didn't at higher power levels.

Sparks look very interesting. With low BPS they are curvy and branched, higher BPS makes a nice wispy flame.




heres a video with the coil running at 60V

I did end up damaging a FET running it at 80V. Interestingly, the FET still works, but it acts as a 60 ohm resistor when it's switched off. The coil still sorta worked with that FET (although not as well), but the FET was getting very warm since it was dissipating 60 watts just sitting there doing nothing. I'm not sure how this happened.
« Last Edit: February 04, 2024, 08:48:30 AM by Lucasww »

Offline davekni

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Re: PLL "IHFSSTC" concept and schematic
« Reply #8 on: February 04, 2024, 09:13:36 PM »
Quote
I did end up damaging a FET running it at 80V. Interestingly, the FET still works, but it acts as a 60 ohm resistor when it's switched off.
Most FET failures are closer to a short, under 1 ohm.  I have occasionally seen such resistive shorts.  No experience with these cascode SiC FETs.  Low voltage silicon FET may have failed partially.  Is the 60 ohms linear with voltage?  Silicon FET damage would result in resistive at low Vds (ohm meter measurement) becoming a constant current at higher Vds (15V and up).

My first guess as to cause is poor thermal contact from package under die to heatsink:
https://highvoltageforum.net/index.php?topic=2191.msg16147#msg16147
David Knierim

Offline Anders Mikkelsen

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Re: PLL "IHFSSTC" concept and schematic
« Reply #9 on: February 07, 2024, 09:49:11 PM »
I'm not totally convinced by the network between the base current transformer and the logic buffer. What's the purpose of the parallel capacitor and series resistor? As drawn, it provides a more or less fixed 90 degree phase shift for small signals, before the clamping diodes are forward biased. When the signal gets larger and the diodes start conducting, it provides a different amount of phase shift, and one that varies a lot with frequency. Given that the range of PC1 is only 180 degrees centered about 90 degrees, it takes some care to keep the plant from exceeding this range (which often leads to latchup with the PLL stuck at one end of the range).

Offline Lucasww

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Re: PLL "IHFSSTC" concept and schematic
« Reply #10 on: February 11, 2024, 06:34:35 AM »
I'm not totally convinced by the network between the base current transformer and the logic buffer. What's the purpose of the parallel capacitor and series resistor? As drawn, it provides a more or less fixed 90 degree phase shift for small signals, before the clamping diodes are forward biased. When the signal gets larger and the diodes start conducting, it provides a different amount of phase shift, and one that varies a lot with frequency. Given that the range of PC1 is only 180 degrees centered about 90 degrees, it takes some care to keep the plant from exceeding this range (which often leads to latchup with the PLL stuck at one end of the range).

From my simulations the circuit seems to work best when the secondary current is in phase with the gate voltage, so the idea was for the parallel capacitor to give a roughly 90 degree phase shift to the current feedback, so that when the PLL locks 90 degrees from that it will be driving the gate in phase with the secondary current. The 1k series resistor should reduce the load from the diodes so that the phase shift doesn't change significantly with the signal strength. It seems to work good enough in practice, but if theres a better way to do this with PC1 I would be interested. As I said previously I don't have all that much experience with PLL.

Offline Anders Mikkelsen

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Re: PLL "IHFSSTC" concept and schematic
« Reply #11 on: February 11, 2024, 10:30:38 PM »
I missed the fact that it was operating around 13 MHz, in which case the situation is a bit better. 47 pF is around 250 ohms at this frequency, so the additional loading from the series 1k and clamping diodes will have less of an impact than I expected, though maybe a bit much for comfort when using PC1. I usually use a D flip-flop together with an XOR gate to unwrap the PC1 range around zero degrees, so it covers -180 to +180, but I also know people had success using PC3 for tesla coil applications. PC2 will not work well when both inputs are frequency-locked together.

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Re: PLL "IHFSSTC" concept and schematic
« Reply #11 on: February 11, 2024, 10:30:38 PM »

 


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February 03, 2024, 07:01:12 PM
post Re: SSTC bus inductance
[Dual Resonant Solid State Tesla coils (DRSSTC)]
flyingperson23
February 03, 2024, 08:04:29 AM
post Re: SSTC bus inductance
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
February 03, 2024, 06:01:12 AM
post Re: is there a standard pinout of optical audio output connectors?
[Electronic Circuits]
Rafft
February 02, 2024, 05:04:44 PM
post SSTC bus inductance
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Benjamin Lockhart
February 02, 2024, 08:34:56 AM
post Re: How much power?
[Spark Gap Tesla Coils (SGTC)]
klugesmith
February 01, 2024, 07:03:41 PM
post Does anyone have a 3d print form for a spiral primary on 4" pvc?
[Solid State Tesla Coils (SSTC)]
yourboi
February 01, 2024, 06:23:45 PM
post Re: How much power?
[Spark Gap Tesla Coils (SGTC)]
Mads Barnkob
February 01, 2024, 07:53:53 AM
post Re: How much power?
[Spark Gap Tesla Coils (SGTC)]
klugesmith
January 31, 2024, 11:43:32 PM
post Re: Welcome new members, come say hello and tell a little about yourself :)
[General Chat]
Ranni81
January 31, 2024, 08:03:40 PM

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