Author Topic: Smoothing capacitor questions on UD 2.7C  (Read 663 times)

Offline Keybored

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Smoothing capacitor questions on UD 2.7C
« on: December 06, 2023, 11:42:18 PM »
Hi all, first time poster.

A couple of noob questions on UD 2.7C - specifically to the power supply smoothing capacitors.  Refer to the diagram https://www.loneoceans.com/labs/ud27/UD27Cschematic.png

Q1.  At the top section, there is capacitors C4A, C4B and optional C4C.   C4A and C4B appear to be both 100uF electrolytics.   Do you get a different result using two smaller 100uF capacitors, than say a single 200uF capacitor?   

Q2.  C35 next to these is 4.7uF but is in-line with Resistor R31.  I have never seen this combination before.  I understand why you want to use small capacitors to take out the high frequency noise, but have never seen it with an addition resistor.  (I assume is 1 Ohm)  Can someone explain why this is done.

Thanks

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Re: Smoothing capacitor questions on UD 2.7C
« Reply #1 on: December 08, 2023, 01:51:32 AM »
I realise Q1 might be one of those 'it depends' type questions, hence the lack of anyone wanting to take shot.  Lower ESR, lower inductance, cost, fitting 2 smaller ones on the board vs 1 big one, redundancy, it works so why change it etc.

Q2 is what I'm really after.

I've even tried simulating it in LTSpice using a white noise generator - but can't seem to notice a difference when I turn R31 into a direct short.  I'm not a LTSpice expect so perhaps I'm doing it wrong.

Offline davekni

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Re: Smoothing capacitor questions on UD 2.7C
« Reply #2 on: December 08, 2023, 08:23:56 PM »
Quote
I've even tried simulating it in LTSpice using a white noise generator - but can't seem to notice a difference when I turn R31 into a direct short.  I'm not a LTSpice expect so perhaps I'm doing it wrong.
Great to hear you are using simulation to answer your question!  I use LTSpice regularly, though never tried a white noise generator.  Are you running a transient analysis (time domain) or an AC sweep (frequency domain)?  For transient analysis, I'd suggest feeding the R+C circuit with a pulsed current source, then plotting voltage.  (Or a pulsed voltage source and plot current.)
I'm not the designer of UD2.7 nor even a user of it.  My answers are thus guesses.  Ceramic caps such as C35 have low ESR.  Some voltage regulator chips (such as IC3) can get unstable with very low ESR output capacitance.  The larger electrolytic caps C4A/B/C usually have enough ESR to keep regulator chip stable.  Most newer regulator chips are stable with low ESR caps (as long as a minimum capacitance value is used).  Thus I doubt R31 is actually necessary.  (Run the simulations anyway.  Good to understand that the resistor actually does change impedance of resulting R+C circuit.)

Quote
I realise Q1 might be one of those 'it depends' type questions, hence the lack of anyone wanting to take shot.  Lower ESR, lower inductance, cost, fitting 2 smaller ones on the board vs 1 big one, redundancy, it works so why change it etc.
All those possibilities are quite reasonable.  I'm not thinking of any other good guesses.  (Low inductance is critical for local chip bypass capacitors and routing to chip power pins, less so for bulk electrolytic bypass capacitors.  So inductance is not too likely a reason.)

Have fun with your TC project!  (Presuming that is what you are using UD2.7 for.)
« Last Edit: December 08, 2023, 08:28:55 PM by davekni »
David Knierim

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Re: Smoothing capacitor questions on UD 2.7C
« Reply #3 on: December 10, 2023, 12:25:37 AM »
Thanks for the response, yes I was using transient analysis and I shall give your pulsed current idea a go.

Just finished my first coil using a slayer circuit
/>
I might try and change it to use a mosfet with a driver, so I can add some interruption down to say 3-10khz - the standard slayer tends to run pretty hot, limiting how much power you can put through it.  I can see how chasing these longer arcs is addictive... Fun stuff.

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Re: Smoothing capacitor questions on UD 2.7C
« Reply #3 on: December 10, 2023, 12:25:37 AM »

 


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