Induction heating II: Shifting the Phase

[Anders Mikkelsen]

PSFB PLL induction heater

I've documented some of my induction heating work in the past here and on 4hv, and here's some more, a bit after the fact as usual.

Having worked extensively with SiC MOSFETs in resonant and hard-switched power converters, I wanted to benefit from their advantages for induction heating as well. For those not familiar with the technology, MOSFETs made in SiC have much lower Rdson per gate charge than their silicon counterparts, particularly if you consider the Rdson coefficient of temperature and compare conduction losses at a realistic operating temperature. This benefit is particularly dramatic at 900 V Vds and above. Another advantage of SiC MOSFETs is that they are immune to latch-up caused by high dI/dt during forced commutation of the body diode, making them much more forgiving when it comes to accidentally losing ZVS in resonant converters. Superjunction MOSFETs have been making a lot of progress on both Qg*Rdson(125C) and commutation ruggedness in the 600+ V class, but at 900+ V there's still little competition.



Anyways,

I wanted to explore new venues of control for induction heating, and providing regulation in the power stage always appealed to me for the simplicity of the power circuit, but this just pushes the complexity to the controls. I already played with PDM so that's trodden ground. Detuning control is simple and it works, but the load power factor is severely degraded when detuning, and this is even worse when driving an LCLR plant. PSFB seemed like a logical choice, as it would also allow the board to control a wide range of resonant loads. QCW Tesla Coils, large HV transformers, fun stuff like that.

The phase shift controller is a classic TI UCC2895, there's not much to say about that part. To wrap a phase loop around it, I use the internal oscillator as a VCO. Frequency is set by drawing a current from the Rt pin, which sits at a fixed 3 V (+- 3 %). By varying the voltage on the other side of the timing resistor, the frequency can be tuned over a reasonable range. Extracting the reference phase from the VCO is a bit trickier, because all the outputs have internally applied dead-time, making them deviate from 50 % duty cycle. It could probably work well enough if the dead-time was set to the minimum value, but I chose to reconstruct the VCO signal from the outputs by using a flip-flop to allow the internal dead-time (and even ADT) to be used as intended. The reconstructed VCO signal is aligned with the turn-off, synchronous to the start of each dead-time event, giving a turn-off current independent of the amount of dead-time applied.

The rest of the PLL is pretty standard. The phase detector is of the XOR type, unwrapped around zero degrees using a D flip-flop. This avoids the common issue of XOR phase detectors locking up when controlling resonant loads, due to the phase shift going outside the linear range of the detector. This is possible to avoid but it needs perfectly balanced propagation delays between the tank current sensing and the bridge voltage sensing at all operating points. It also avoids the latchup problems of the 4046 "type-II" phase detector with 720 degrees of memory, which can lock up if any extra edge is seen on either input. The implementation is a bit weird, using 2/3 of a 74HC4053 to realize an XOR gate with output enable. This was the best idea I came up with to do this in a single off-the-shelf IC, with 1/3 of the chip left unused to boot. The leftover section was used along with a leftover comparator to generate the two-phase drive for the isolated gate drive power.

I separated out the tank current phase sensing (used for the PLL) and the bridge current sensing (used for the phase shift control loop), to allow use with both (transformer coupled) series resonant and LCLR type tank circuits.  To allow the CTs to be placed on the control board without heavy wiring, and to allow the use of stock CTs with a limited sensing range, capacitive dividers are used to only sense a fraction of the real current.  For series resonant, both CTs can be connected in series with a cap across the output DC block. For LCLR, the phase CT is connected in series with a small cap across the tank capacitor, while the current regulation CT is connected in series with a cap across the DC block.

The gate drive scheme is probably what I spent most effort on. I was looking into using GDTs to drive SiC transistors with their asymmetrical gate voltage requirements. SiC JFET cascodes can solve this as they have a traditional Si MOSFET as their controlled device, but I already had good stock of Wolfspeed C3M series devices in TO-247-4. Steve Conner proposed a clever circuit, where the positive gate voltage was passed straight through, while the negative gate voltage was divided by resistors and buffered by a common collector stage. The trick worked, but getting good dynamic behavior was a balancing act, and startup behavior was a bit dodgy. I have good experience with galvanically isolated gate drivers (as long as they have a high enough CMTI rating, 100+ V/ns recommended for SiC) so I opted for those. That leaves the challenge of powering them.

Each gate channel needs +15 and -4 V, with very low isolation capacitance (picofarads pass hundreds of milliamps at these edge rates), high CMTI rating and decent regulation. There are off-the-shelf modules from Murata and Recom that do the job, but where's the fun in that? I decided to base the supply on off-the-shelf gate drive transformers, due to their low cost and decent isolation ratings, more specifically the Pulse P-0584 series. Splitting the rails is easily done using a low current zener regulator with solid decoupling, as the midpoint doesn't need to support any DC current. This just leaves the question of how to drive the primary to generate two 19 V rails with good cross-regulation and load regulation. An isolated charge pump with voltage doubling on the outputs seemed like the simplest choice. Since the charge pump doesn't provide any opportunity for regulation using duty cycle, a buck was used to feed the bridge, which was just a regular gate drive IC. After some tuning, this ended up working pretty well. Gate drive ICs that use a small MOSFET stage in parallel with a BJT stage don't work well here, the line regulation is pretty bad due to the non-linear output resistance of the device. The secondary diodes also play a large role in load regulation, and the part with the smallest Vf(100 mA) - Vf(10 mA) was chosen after evaluating a bunch of options. The BAV99 won out, this is my new favorite small signal diode.

Schematics of the control board are here: pll_controller_1.pdf Note that some component values are not final and the whole design is experimental.



The control section was done on a separate board, to allow the use with different size and form factor power stages. The schematic and layout was done in Kicad, across a few evenings during lockdown. Some people solve sudoku puzzles, I like to route dense boards. In addition to the circuitry described above, an isolated DC bus sense section was added, to allow output power control. Natively, the board provides primary current regulation controlled by an external DC voltage. An external enable/disable line controls operation of the controller.




A power board with a 3-phase rectifier and a SiC-fullbridge was put together to test the design. With the moderately small 65 mohm 1000 V devices used, it should be able to handle maybe 25 A RMS out, for which the DC bus and DC blocking caps are dimensioned. It can run with a DC bus voltage of up to 800 V, though more practical will be to run it directly from 400 V 3 phase mains, where power factor should be close to the theoretical 0.95 due to the minimal DC bus filtering. Power at unity load power factor should be just north of 10 kW with 400 V 3-phase in. I expect it can provide this at 250+ kHz, from previous experience with the same devices. More devices will allow power levels up to 25+ kW, where gate drive requirements start to become problematic at higher operating frequencies. Going to 50 kW and beyond at 100 kHz should be doable.



This leaves the biggest topic, which is also one of the reasons I'm posting this project here. How do you tune the current and phase loop to work well over a realistic range of tank impedances, Qs and resonant frequencies? I went with type II compensators for current and phase, and placed the poles and zeroes by ligthly qualified guessing. The PLL compensator zero was placed below worst case F0/Q, and the pole was placed significantly above the highest expected F0/Q. The current loop compensator was placed a decade or so below the phase loop one, to hopefully avoid too many interactions. This almost worked, showing that both phase and current loops can be made to work together, but it was breaking out into instability at certain operating points. Some semi-qualified tweaking to values didn't seem to improve the situation. I realized that I'm a bit out of my comfort zone when it comes to control theory, particularly with the two loops potentially interacting and how this impacts stability. I started reading up on it, but this also killed a lot of my motivation for the project and I ended up putting it in a box and working on something more fun. It's been a over a year, and it would be a waste to just let it die there.

Here's a short video of when it was working with both loops active, driving an LCLR tank. Yellow is tank voltage, purple is output voltage, blue is primary current. Some load is placed into the tank coil, changing both the Q and F0, and the controller can be seen to track both.

My main plan now would be to disable the current loop and try to tune the phase loop on its own, maybe characterize the open-loop response of the current controller with the phase loop active, before trying to close the current loop. Is this a sensible approach, or am I missing something? All and any tips that the community can provide on how to proceed are appreciated, if only to help me understand the depth of this hole.

[Weston]

Really cool work! I really like the isolated gate drive power supplies. This looks like it should be a really capable high power system.

When the plant parameters vary a lot you sometimes see controllers that can dynamically reconfigure the control loop, but that is hard to do with an analog controller.

Having the cross over frequencies for the two controllers be at widely spaced frequencies should work. When you are seeing the system oscillate is it at conditions in which there would be reduced spacing between the cross over frequencies of the two control loops?

Cascaded control loops, like in average current mode converters, are easier to model than this, where the control loops are operating in parallel. The active control loop will change the response of the plant for the other control variable. Your approach of measuring the open loop response for the current loop while the phase loop is operating sounds like a solid approach, its the first thing I would try.

Can you just move the cross over frequency for the power control loop to some very low frequency? I assume if you want the power factor to be good it already has to be less than the AC line ripple frequency.