GDT Testing

[ZakW]

Hello,

Back again with more questions after Google was unable to help. I received my function generator and have been testing my 74HC14/CT feedback circuit to make sure everything is working correctly. Now that that is done I wanted to test my gate drive portion to ensure the GDT wiring and setup is optimal.

The issue I am running into now seems to be related to the output of the UCC3732x IC's. Like the output current is insufficient to handle the load. However, this appears to be happening regardless of the load amount, GDT turns, and frequency.

Test setup:



I plan on driving a full bridge of IRFP460's. So for a test load I am using a 100nf cap. I calculated the load by using the IRFP460 data sheet info - (Q_g/V_gs)*1.5 (50% margin)*4(# of FETS)=> (210nC/10v)* 1.5*4 = 126nf (rounded down a bit to 100nf).

SSTC secondary F_res ~470kHz (that is what I was testing at)

GDT core type = T35 https://www.mouser.com/ProductDetail/871-B64290L618X35

Amount of turns tested: Inductance measured with RLC meter

- 16T = 1.5mH
- 15T = 1.31mH
- 4T = 68.8uH

Capacitor load test values used:

15nf - to approximate 1 MOSFET
55nf - to approximate a half bridge (2 FETS)
100nf - full bridge

Dampening resistors tested:

1-5 Ohms - always resulted in a very over dampened waveform even when only using 1ohm.

Observations:

UCC output and GDT output are perfect without a load
yellow=GDT
purple=UCC



At first the measured output when using a 100nf cap appeared to be a sine wave. When I scaled the frequency down however, I began to see a more squarish wave. That did not start to appear until 100kHz or less. After many different test setups I decided to look at the output from the UCC IC's. From the scope pictures the UCC output signal (purple) seems to be slowly charging the capacitor which I think is causing the poor output.

What confuses me is that these are rated for 9 amp's and when testing with lower loads i.e. 1 MOSFET @ 15nf I still get a very bad output. Therefore I think the issue is related to my UCC IC's and how they are being powered or connected? Additionally, this is the same driver board that I was able to run a half bridge and full bridge with. Although the performance was not great so that is why I am testing it now.

Troubleshooting so far:

- Replaced the UCC IC's = same issue
- Added additional bypass capacitors 0.1uf & .01uf (ceramic) = no noticeable impact
    - existing bypass caps are film caps (red) figured I would try to ceramic instead
- Used different DC blocking capacitor values on the UCC output - 2,2uf and my original setup 2uf with 2 47uf electrolytic caps = no noticeable impact
- Shortened lead lengths to and from GDT =  no noticeable impact
- Tested a different core material = same results
- Tested at different frequencies from 470kHz to 10kHz - the 'dip' in the UCC output seemed to get better sub 150kHz but never fully went away
- Tested at different capacitive loads - unloaded, 15nf, 55nf, 100nf = The smaller the load the less distorted the output is
- Different dampening resistors used = caused the 'shark fin' appearance every time regardless of cap load value
- added a 5ohm resistor on the UCC primary side = no noticeable impact
- added 1uf Electrolytic caps to power pins of the UCC's = no noticeable impact



The red circle - is that the UCC output charging the load cap before discharging? Other than adjusting the frequency I cannot seem to get rid of this.


Next steps and questions:

- I could create a new UCC driver pair on a separate board to rule out any soldering/layout mistakes
- I could connect the GDT output to my half bridge and test the gate and source signal at the FET (I have to rebuild it so that is why I did not test it yet)
- Any ideas on what might cause this output from the UCC's? Is there a mistake in my test setup causing this behavior?


I uploaded additional photos for reference. They are all labeled so hopefully that should provide enough context. For consistency sake - yellow is GDT output and purple is UCC output.

Thank you!

[davekni]

I think your driver will function well with real GDT wound with 4 twisted pairs and proper gate series resistors (around 5 to 10 ohms each gate).  Your 100nF calculation is good.  Here's my 2-output GDT example with links to 4-output versions made the same way:
https://highvoltageforum.net/index.php?topic=1854.msg13949#msg13949
Total leakage inductance of the 4 pairs will be roughly 1/4th of your 1 pair test GDT.

There has been a rash of counterfeit UCC driver chips, but they appear to function except for enable input.  Not likely your issue.

I presume you are running the driver at 12V, not 15V per schematic.

UCC output stage is a bipolar/MOS combination.  Output impedance is much higher close to supply rails than would be implied by 9A peak current.  That is part of the strange shape you see on UCC output, especially the rising transitions.  Remainder is likely wiring inductance on your breadboard.  That breadboard contribution will not go down with the 4-twisted-pair GDT.  Probably OK still.

Additional bypass capacitance at the UCC chips is always a good idea, especially with breadboard construction (no ground or power planes).  I'd suggest at least 0.47uF at each driver chip.  (1uF electrolytic capacitors likely have too high ESR, so likely need to be larger if electrolytic.)

At 470kHz you can use fewer GDT turns.  That reduces total twisted-pair wire length, reducing leakage inductance.  4 turns is likely good, though the minimum depends on ferrite core size and saturation flux density.

[ZakW]

Hello Dave, thanks for taking a look.

I think your driver will function well with real GDT wound with 4 twisted pairs and proper gate series resistors (around 5 to 10 ohms each gate).  Your 100nF calculation is good.  Here's my 2-output GDT example with links to 4-output versions made the same way:
https://highvoltageforum.net/index.php?topic=1854.msg13949#msg13949
Total leakage inductance of the 4 pairs will be roughly 1/4th of your 1 pair test GDT.

What I don't understand still is why I am getting these results? Is simply substituting a capacitor as a test load that much different from driving an actual MOSFET? How do others test GDTs? The point of testing the GDT with various loads was to find the correct number of turns required before making the final full bridge GDT. I wanted to see the impact of too many turns via my scope to learn more about what is happening in real time. 

I was only using a bifilar winding for testing. Since I planned on removing turns and comparing results along the way I didn't see the need to wind the other FET connections. (primary and secondary for testing)

I am glad the 100nf is okay. I have referenced your post on winding GDT several times. Thanks for documenting it clearly, it was very easy to follow. Rest assured I wound a new GDT following your advice, I was just wanting to test the core/operating frequency first to find the ideal amount of turns.

There has been a rash of counterfeit UCC driver chips, but they appear to function except for enable input.  Not likely your issue.

I agree, I do not think this is my issue either. I get all of my parts from Mouser and never have I had a problem with the enable pin not working.

I presume you are running the driver at 12V, not 15V per schematic.

Actually, I am using an LM7815. I figured the few extra volts might improve drive as the UCC's would be powering a full bridge. To reduce the potential of damaging the gate due to excess voltage I plan on swapping it out for a 12v regulator.

UCC output stage is a bipolar/MOS combination.  Output impedance is much higher close to supply rails than would be implied by 9A peak current.  That is part of the strange shape you see on UCC output, especially the rising transitions.  Remainder is likely wiring inductance on your breadboard.  That breadboard contribution will not go down with the 4-twisted-pair GDT.  Probably OK still.

I have made several breadboard layouts before and have had decent results. I was thinking this should be my best yet but it has not performed that way so far. I tried keeping the power rails as neat as possible, especially the ground connections.

Additional bypass capacitance at the UCC chips is always a good idea, especially with breadboard construction (no ground or power planes).  I'd suggest at least 0.47uF at each driver chip.  (1uF electrolytic capacitors likely have too high ESR, so likely need to be larger if electrolytic.)

I will give .47uf caps a try instead of the 1uf.

At 470kHz you can use fewer GDT turns.  That reduces total twisted-pair wire length, reducing leakage inductance.  4 turns is likely good, though the minimum depends on ferrite core size and saturation flux density.

Good to know I will likely need fewer turns. Like I mentioned before, the plan was to arrive at the optimal # turns based on testing.

[davekni]

Actually, I am using an LM7815. I figured the few extra volts might improve drive as the UCC's would be powering a full bridge. To reduce the potential of damaging the gate due to excess voltage I plan on swapping it out for a 12v regulator.

Then something more is wrong.  The unloaded scope traces show 11V output swing from the UCC.  It should be 15V.  A part of that discrepancy appears to be mis-adjusted scope probe compensation.  Fixing that likely would show 12-13V swing, still below expected 15V.  I recommend finding and fixing this issue in case the cause is related to other behavior.  (Perhaps your incoming DC supply is only 15V, so the LM7815 can't output more than ~13V.)  Yes, I'd recommend 12V for driving FETs.  Especially at your high 470kHz, driver chip heating may be problematic at high duty cycles, even more so at 15V.

I was only using a bifilar winding for testing. Since I planned on removing turns and comparing results along the way I didn't see the need to wind the other FET connections. (primary and secondary for testing)

With the entire 100nF load on one GDT winding, that winding's leakage inductance has 4x current flowing through it, so will make larger artifacts.  If you want to continue testing this way, at least add ~2ohms in series with 100nF.  Waveform will be overly rounded, but look more normal.

What I don't understand still is why I am getting these results? Is simply substituting a capacitor as a test load that much different from driving an actual MOSFET? How do others test GDTs? The point of testing the GDT with various loads was to find the correct number of turns required before making the final full bridge GDT. I wanted to see the impact of too many turns via my scope to learn more about what is happening in real time.

For testing GDT, a single FET load is appropriate for a single twisted-pair winding, so ~22nF with 5-10 ohms in series.  High-turn limits do need the load to show up.  Optimum damping resistance will increase with turns (with total twisted pair length including leads).  For low-turn limit, no load is necessary.  However, test at half operating frequency to accommodate initial startup pulse where current from previous pulse is missing.

I have made several breadboard layouts before and have had decent results. I was thinking this should be my best yet but it has not performed that way so far. I tried keeping the power rails as neat as possible, especially the ground connections.

Have any previous breadboards switched this much current (9A peak) this quickly?  Yes, your breadboard construction looks very neat, better than most of my projects.  Neatness usually implies short connections, which helps.  However, connections cannot be short enough to match the low inductance of parallel overlapping copper planes.  These days almost all of my hand-constructed circuits are built with at least a ground plane under the entire circuit.  As I said, your build is likely good enough.  However, parasitic inductance is part of the signal anomalies you are puzzling over.  Other part is the odd output impedance behavior of UCC chips, which unfortunately is not well specified.  Adding an appropriate series damping resistor to your 100nF test load will help somewhat with odd UCC output waveform behavior.

[ZakW]

Then something more is wrong.  The unloaded scope traces show 11V output swing from the UCC.  It should be 15V.  A part of that discrepancy appears to be mis-adjusted scope probe compensation.  Fixing that likely would show 12-13V swing, still below expected 15V.  I recommend finding and fixing this issue in case the cause is related to other behavior.  (Perhaps your incoming DC supply is only 15V, so the LM7815 can't output more than ~13V.)  Yes, I'd recommend 12V for driving FETs.  Especially at your high 470kHz, driver chip heating may be problematic at high duty cycles, even more so at 15V.

Good eye! I forgot to mention that in my original post. I am powering the logic side with a laptop PSU and I wanted to rule out any issues with the supply so I connected my bench top power supply to the input. Nothing changed so I decided to try lowering the voltage to ~12v to see if maybe the 15v was causing issues. That's why the scope pictures show less than 15v.

I will swap out the regulator for a 12v version.

With the entire 100nF load on one GDT winding, that winding's leakage inductance has 4x current flowing through it, so will make larger artifacts.  If you want to continue testing this way, at least add ~2ohms in series with 100nF.  Waveform will be overly rounded, but look more normal.

That makes more sense now - I did try adding a resistor and you're correct, the waveform was overly rounded.

For testing GDT, a single FET load is appropriate for a single twisted-pair winding, so ~22nF with 5-10 ohms in series.  High-turn limits do need the load to show up.  Optimum damping resistance will increase with turns (with total twisted pair length including leads).  For low-turn limit, no load is necessary.

If I understand correctly, are you saying a more real world measurement would be to probe the GDT when it is connected to a single MOSFET to approximate the final output? Rather than trying to do it all at once and having to deal with leakage inductance being multiplied many times over skewing measurements.

However, test at half operating frequency to accommodate initial startup pulse where current from previous pulse is missing.

If plan on the running the coil at ~470kHz the GDT not only needs to work at that frequency but also at half of that (~235kHZ)?

Have any previous breadboards switched this much current (9A peak) this quickly?  Yes, your breadboard construction looks very neat, better than most of my projects.  Neatness usually implies short connections, which helps.  However, connections cannot be short enough to match the low inductance of parallel overlapping copper planes.  These days almost all of my hand-constructed circuits are built with at least a ground plane under the entire circuit.  As I said, your build is likely good enough.  However, parasitic inductance is part of the signal anomalies you are puzzling over.  Other part is the odd output impedance behavior of UCC chips, which unfortunately is not well specified.  Adding an appropriate series damping resistor to your 100nF test load will help somewhat with odd UCC output waveform behavior.

Thanks for the compliment! If you have pictures and would not mind sharing I would like to see how you added the ground plane to your hand-constructed circuits. Are you referring to supergluing little pads on top of the ground plane and making all of the connections on them?

I made Steve SSTC5 mini way back on a breadboard but it was running around 350kHz. So this is the highest Fres I have run a full bridge at.

Sounds like the combination of inductance that is inherent in a breadboard style design plus trying to measure the out put waveform for all 4 FETs (100nf) is too much to do at once. I will test again, measuring the result at a single MOSFET and see what the results are.

Thanks for the advice!

[davekni]

Quote

    For testing GDT, a single FET load is appropriate for a single twisted-pair winding, so ~22nF with 5-10 ohms in series.  High-turn limits do need the load to show up.  Optimum damping resistance will increase with turns (with total twisted pair length including leads).  For low-turn limit, no load is necessary.


If I understand correctly, are you saying a more real world measurement would be to probe the GDT when it is connected to a single MOSFET to approximate the final output? Rather than trying to do it all at once and having to deal with leakage inductance being multiplied many times over skewing measurements.

Yes, exactly.

Quote

    However, test at half operating frequency to accommodate initial startup pulse where current from previous pulse is missing.


If plan on the running the coil at ~470kHz the GDT not only needs to work at that frequency but also at half of that (~235kHZ)?

Half frequency (235kHz) comes from the need to start and stop with enable pulses.  Normally, GDT magnetic flux is zero at the centers of the positive and negative half-cycles.  It is maximum at the voltage transitions.  Flux is a triangle wave, the integral of GDT voltage square wave.  Each half-cycle starts with flux in one polarity, ramps to zero, and then to the opposite polarity.
However, for the very first half-cycle, flux is starting at zero.  The ramp peak-to-peak is the same, so it ramps from zero to 2x normal peak flux (rather than from -1x to +1x).  Startup at 470kHz is the same peak flux as continuous operation at 235kHz.

hanks for the compliment! If you have pictures and would not mind sharing I would like to see how you added the ground plane to your hand-constructed circuits. Are you referring to supergluing little pads on top of the ground plane and making all of the connections on them?

There are many techniques.  Here are links to a few commercial breadboard products with ground planes.  I've used some similar ones, but not these specific versions (only internal Tektronix or Xerox boards from my work):
https://www.sparkfun.com/products/retired/8815
https://www.amazon.com/SMT3U-SMTboard-3U-Sided-Unplated-Ground/dp/B0040Z1FVE
https://www.tindie.com/products/SpeedyLab/prototype-pcb-board-with-ground-plane-3/
https://www.kickstarter.com/projects/pnmini/speedyproto-the-only-protoboard-with-a-ground-plan
For discrete transistor work (and occasionally SMD ICs), I often start with bare double-sided copper clad, using back side for ground and top side for circuitry, cutting top-side copper with Dremel tool:

This isn't a high-voltage board, just an example of technique.  Cuts are with a small rotory-tool cutoff wheel, with edges cleaned up using a knife and light sanding to finish.

Finally, ECBs are surprisingly cheap and fast ordered from China.  Shipping is much more expensive than the boards themselves, at least for simpler designs.  Even 4-layers is reasonable.  I use:
https://www.allpcb.com/

[Mads Barnkob]

Thank you for making a high quality trouble shooting thread, a prima examples for everyone to follow! Loads of information and pictures

Having read through the thread, and looking at all the waveforms at different frequencies, it is also parasitic inductance ringing that pops up in my head.

I train as I fight, so just connect a half-/full-bridge of MOSFETs with correct gate resistors, no reason to waste time on approximations.

If you insert a USB drive in your scope and press the printer button, it will quick save the screen content, if you are tired of taking photos of the screen

[ZakW]

Thank you for making a high quality trouble shooting thread, a prima examples for everyone to follow! Loads of information and pictures

Hello Mads, thanks for saying so. I figure if I am asking for help I should try and provide as much relevant information as possible.

Having read through the thread, and looking at all the waveforms at different frequencies, it is also parasitic inductance ringing that pops up in my head.

I think you and Dave are correct in that testing a single bifilar winding with 100nf is too much especially given the lead lengths as well as the inherent parasitic inductance of my driver output due to the breadboard construction.

I train as I fight, so just connect a half-/full-bridge of MOSFETs with correct gate resistors, no reason to waste time on approximations.

I agree with that. That is my next step after I re-design my driver and interrupter. I am planning on creating proper PCBs this time so it will take a me a bit though.

If you insert a USB drive in your scope and press the printer button, it will quick save the screen content, if you are tired of taking photos of the screen

I have done it that way in the past but I feel like it's a little faster with my phone and the quality seems alright for my purposes. Plus uploading to Google drive and uploading images to the thread is pretty quick too.

[johnf]

If you have two identical cores make two and put them back to back
then run some power at various frequencies through them, losses are exacerbated by a factor of two so it should be easy to see