cute-qcw Tesla Coil

[Weston]

Hi All,

I have been working on a FPGA based qcw tesla coil driver for the past 3 months, documenting photos on flickr and posting all the PCB layouts / code on github. Right now the secondary is a bit big compared to many QCW builds (12" tall), but I intend for the coil to be small eventually, so I called the project cute-qcw. The end goal is a compact version of the coil to mount on the front of a bicycle for Burning Man.

I had first light earlier this week and I ramped the coil up to full power for the first time earlier today.

Now that everything works I figured its time to share the project.

The secondary is 12" tall and I am running at the upper pole of ~390KHz, with the secondary tuned above the primary. This puts the gain of the lower pole higher than the upper pole, which can make it difficult to drive with a direct feedback controller. My driver uses a digital PLL and forces ~20 RF cycles at a fixed frequency at the start of the burst to lock on to the upper pole.

Here is a photo to catch your attention:


Github repo is here: https://github.com/westonb/cute-qcw
More photos here: https://www.flickr.com/photos/63341195@N08/sets/72157678478822788/with/47390843571/

I am going to be documenting everything a bit better on github in the next few weeks. Please ask questions if you have any.

[flyglas]

Hi Weston,
your PCBs are looking very good. I like your H-Bridge, MCC and FPGA board design!
I am currently at a very similar project, but I do not have pictures online and my code is not finished (no first light).

What is your interal frequency of the FPGA?

[Weston]

I forgot to say, but the coil uses a phase shifted fullbridge for modulation. Right now I am running at a 10ms burst and hitting a peak tank current of ~60A.


The FPGA logic runs at 240MHz. It may have been due to some other factors which I eliminated in debugging, but I was having issues with PLL stability which I thought may have been due to the limited frequency resolution of the counter generating the gate drive signals, so I bumped it up to 240MHz from 160MHz. 

I think my PLL may occasionally still be mis-locking, causing the coil to operate in some mode that leads to primary - secondary flashover. I managed to capture waveforms of both a normal discharge and a flashover (yellow: inverter voltage, blue: current), when it flashes over you can see that there is a high current pulse, but from the start of the pulse the current is lower, implying that something is wrong with the pulse from the start.

Normal Pulse:

Flashover Pulse:

[flyglas]

Hi Weston,

is a PLL really necessary?
The first 20 RF cycles with a frequency given by the FPGA (the upper pole frequency of the resonant sytem programmed into the FPGA) are possible without a PLL. After that the system should stay at this frequency if you commutate the bridge with the signal from the ZCD.
I am right?

[Uspring]

I'd attribute the differing primary currents in your two scope shots to differing arc loads. Those can arise from differing tuning situations, particularly different driving frequencies. Have you had a look at these? In the case of low primary currents, the frequency is probably closer to the secondary resonance frequency, since that leads to a better transfer of primary energy to the secondary, which reduces primary current.

In the second scope shot, the sudden rise of primary current looks like the coil is suddenly going out of tune.

[Weston]

Some mechanism is needed to provide phase lead and allow for zero current switching.

In some designs inductive loading is added to the CT so provide phase lead in the analog domain. The UD 3.0 driver adjusts a timer to switch the inverter based on the timing of the last ZCS transition, which is similar to a phased locked loop approach. Other FPGA based controllers have implemented phase lead in the digital domain with a FIR/IIR filter, but this requires more logic resources and a high speed ADC.


The two scope shots are with the same system parameters. I suspect that some noise is causing the PLL to lock on to some other operating frequency that leads to a different voltage distribution on the secondary and leads to the flashover between the middle of the secondary and the primary. I think that the flashover itself is leading to some system parameters changing (secondary effectively partially shorted),  and the PLL tracking this new resonant mode causes the sudden increase in current.

I suspect by altering my PLL loop gain and adding a bit more digital filtering of the ZCS signal I can eliminate this issue, but I will see if I can get higher resolution scope shots showing that frequency the PLL is locking on to.

[Mads Barnkob]

Hi Weston and welcome to HVF

I think the only compliment I have here is industrial grade quality and open source hardware/software is heartwarming.

How does one go about BGA soldering without the special gear for it? I mean would I get away with using a regular heat gun and fixing the IC in place with some kind of holder? This is where I like the designs that can use a dev board to plugin as it makes it easy for all kinds of amateurs to take on the design.

Thanks for sharing and really looking forward to what you can push this design to perform.