First SSTC build - some questions

[davekni]

I'd forgotten about the 1.5:1 GDT ratio directly from a driver chip.  That explains why Vge waveforms have slower transitions with full-bridge load on the driver chip.

[zytra]

I meant to post this one before and forgot. It's with nothing on the bus, i.e. what I suspect is the resistor across pins 1 and 2 of the inverter, to initiate an oscillation. I was thinking about this last night and I remembered how the oscillations looked comparable to the low frequency ring.

[zytra]

And here are a few (same waveforms with different time scales) with the bridge DC blocking cap added.
It did fix the symmetry on the current waveform. And it also seems like it's crossing to be switching quote a bit softer too (especially on rising current).

 

[davekni]

I think that no-bus-voltage plot shows the resonance is GDT with blocking capacitor.  The oscillation frequency of the 20k resistor and feedback 0.1uF capacitor is too low to show even a half-cycle during that scope capture.  (The 20k still serves a purpose, keeping the feedback voltage near the HC14 threshold.)  Adding the R+C damping across the 1uF GDT input DC blocking capacitor should reduce that ring to a half-cycle or so.

The other traces all look fine.  Vge transitions are on the slow side, but probably OK.  Not much that can be done without changing to a UD2.7 or similar driver with higher current and voltage GDT drive capability.

[zytra]

Yes, the gates traces aren't as steep as they were with the half bridge. It won't hurt, but perhaps affects performance a little bit. I spent some time gathering data for various numbers of primary turns. Nothing really conclusive, I'll post about it later after I look at the numbers in more details.



By the way I didn't mention but that nothing on the bus screen capture triggered off the end of a pulse (i.e. when the enable pin of the driver goes low). It does oscillate for a while.

As opposed to the same capture but this time captured off a rising pulse (when the enable pin goes high, see attached screenshot where we can see both oscillations at the beginning of the pulse and at the end). Weirdly enough, it doesn't oscillate for nearly as long.

Tomorrow, I'll add the RC damping you mentioned.

edit: I just remembered, I had the same waveform on the scope (when nothing was on the Vbus) with the half bridge and more importantly with the previous GDT. Although, it's not impossible that both GDT's would resonate with the DC blocking cap at roughly the same frequency, how likely would that be though?

Also, looking how that low frequency ring affects the shape of the current waveform, how likely is it that it affects performance?

[davekni]

That GDT resonant frequency depends on GDT primary inductance and the 1uF DC blocking capacitor.  If the GDT cores were similar and the primary turns-count similar, then the frequencies will be close.

The GDT ring at the end has little energy to excite it, just the final half-cycle of normal oscillation.  At the beginning with no bus voltage, it has a full 12V step for a long period compared to the oscillation cycle.

[zytra]

I've meant to gather data at various primary turns for a few days and finally got around to doing it today.

- Measuring arc length wasn't easy and should be pretty much be ignored, and I can't even objectively say that there was any difference in length. I had a ruler against the wall behind, and stood as far as I could to minimize parallax. Then I would wait a little for arcs to discharge along the length of the ruler. Yeah, not the best protocol but I wasn't looking for accurate length either.
- I also measured current draw at the wall, PF and power. No calculations here, just readings off a cheap wattmeter.
- All tests were done with 110VAC to the rectifier/doubler, 10Hz and 1ms pulses.

I started from 20 turns and then went down 2 turns at a time. It's only when I got to very low number of turns that I thought about checking the P2P current in those pulses, to realize they were significantly higher. I quickly wrote down that value for 6 turns, repeated the test for 20 turns, put those down as notes in the table.

I was a bit surprised that although the primary current was significantly higher for 6 turns, it wasn't higher at the wall at all. Considering the power draw was so small overall I think most of current draw at the wall basically are losses, with very little actually going into an arc. I could measure what's actually going in the primary by pulling the RMS current since we know the bus voltage; this way I could compare.

After those tests, I set the number of turns to 11, at least for now.

edit: sorry posts crossed. Thanks, we'll know for sure tomorrow once I had damping! Thanks

[davekni]

Higher primary current without higher wall current suggests that primary current and voltage are farther out-of-phase with 6 turns.  Can't tell at that zoom level.  Since performance is similar, 20 turns is much easier on the bridge.

I like your quantitative characterization of performance.  Measuring secondary coil current may provide a more repeatable indication of coil performance for optimization.  It is also useful to compare secondary current phase with primary voltage phase.  If too far off, performance will suffer.  Your after-zero-current switching is (I think) uncommon for SSTCs, and may indicate mismatched phasing of primary voltage with secondary current.

[zytra]

I may be a bit too cautious, but I'm trying not to kill the coil or at least maximize time between repairs so I can gather as much data as possible to hopefully make sense of the physics behind all this. But I think my 1% duty cycle is just too little, that is for the tests I ran today. I am trying to not push more than 1ms pulses (which is what I deducted as a safe pulse duration from the IGBT datasheet). And since experimentally 10 Hz, 1% (1ms) gives me the longest arcs (rather, the best ratio of arc length over power consumed), they became my go-to tests parameters.

My secondary system is probably a little bit on the high side in terms of impedance (60kHz). By the way, running longer pulses is something I've tried for quick tests and they do help a lot, making arcs thicker and deeper. They appear longer but not sure if they actually are or if they just appear that way being so much brighter.

I've put the current probe on the secondary a few days ago just to have a look, I'll do that again and correlate that to primary voltage. I do wonder if this phasing is dependent on spark load.

One thing that has been consistent throughout all the tests so far is the shape of the current pulses. Aside from that low frequency ring, regardless of the enable parameters (frequency/on time) I always get that "blob" that's usually right in the middle of the low frequency ring. The shape of the blob will vary slightly based on the bus voltage (and as seen today, by the primary turns). What is causing the current waveform to have a stronger P2P in that early region of the pulse? I understand why it takes some time for the current waveform to get a certain regime (i.e. the feedback loop to lock on the resonance frequency), but then why does it drop/stabilize lower? Spark load will affect the resonant frequency but the feedback is there for that. And it can't possibly be capacitors discharging considering the energy stored and the fact that it does stabilize for the rest of the pulse, a cap discharging wouldn't - the time scale of those pulses (1ms) is a fraction of the mains' period.



Edit: I calculated an inductance of 24 uH for the primary as it currently is now. At 117 kHz (measured from screen 90) it should yield a reactance of 17.5 ohm, which at 320VDC should mean a peak to peak current of 18.5A or so. I measured (screen94) ~40A peak to peak away from the initial blob... I'll check my probe - seems like a big discrepancy if we consider the 40A - but on that screenshot the blob peaked over double that value. That same primary, with the 4.7uF DC blocking cap has a resonant frequency of just under 15 kHz, which incidentally still matches the low frequency ring. I'll have to measure it more accurately. Maybe I'll try a more tightly coupled primary again. You said the GDT might resonate with the driver's DC blocking cap, how would that cause the primary current to react that way, the primary circuit would need to resonate with that as well, wouldn't it?

[davekni]

Spice simulations can provide great insight to what's happening.  It can be tricky to know what details need to be modeled.

I expect the initial higher-primary-current "blob" is caused by high-Q secondary resonance and associated (induced) high secondary current.  As the arc grows, it adds capacitance, but also resistance in series with that capacitance, which reduces Q.  Lower Q drops secondary current, which reduces induced primary current.  It is that induced current from the secondary that allows primary current to rise well above what it would be with no secondary in place.

My guess is that the arc stops growing when current settles after the blob.  The arc likely reaches an equilibrium, dissipating as much power as it is being fed.  It might be interesting to try shorter (perhaps 0.5ms) enable pulses at a higher repetition rate.

For simulating the arc, it is easiest to run separate simulations for different arc lengths, with different resistances and capacitances.  It is possible to model changing resistance and capacitance.  I've done that for my DRSSTC, but don't have accurate information on how resistances and capacitances change as a function of voltage and time.

Concerning GDT resonance showing up on primary current, I think it is related to the relatively-slow slopes on Vge waveforms due to driver chip output impedance.  As GDT current rings, it will pull Vge duty cycle higher and lower.  If the primary coil and blocking capacitor happen to resonate at the same frequency, that will amplify the current ring.  Simulation would show if that is likely as long as driver output impedance and GDT inductance and coupling factor (leakage inductance) are modeled.  Adding GDT DC blocking capacitor damping will also verify if this is the cause of primary current ring.

[zytra]

Thanks Dave, I have started playing with LTSpice. I'm sure it will be a great tool once I am more familiar with it.

Your explanation on the "blob" makes sense; I'll now test the damping theory for the GDT DC blocking.

[zytra]

The 20 ohm + 1 uF in series of the existing 1 uF DC blocking cap on the GDT didn't help, in fact it looks like the waveform hasn't changed, and the low frequency ring is still there.

I've made a short video which will show a bit more how that current waveform evolves from 0VAC to 110VAC: https://www.youtube.com/watch?v=_LIvVoRE4zg&feature=youtu.be

here's the current state of performance: https://www.youtube.com/watch?v=GMmQSiZCmdc&feature=youtu.be

[davekni]

It is clear that at least by now the GDT resonance isn't a significant factor in primary current ring.  Looking back, it was clear in your reply#86 too.  The primary ring is dominantly ~12kHz.  The GDT ring was ~5.5kHz before, and ~4kHz now (as expected with the added cap and resistor).  Looking back at older plots, primary current ring has some lower-frequency components, which might have been GDT related.  Now there is little 4kHz visible.  (At 4kHz, 1uF is ~40 ohms, so perhaps the series resistor would be better around 40 ohms instead of 20.)

24uH primary with 4.7uF DC blocking would resonate at 15kHz.  So that is likely a factor in the latest ring plots, at least magnifying any other ring-inducing factor.  Not being a DRSSTC, I can't think of any beat frequencies that would cause the ring.  You could try adding damping to the 0.1uF.  Perhaps another 0.1uF in series with ~200 ohms.  And/or, you could test changes and/or damping on the 4.7uF primary DC blocking capacitor.  Much of this would be aimed at experimenting/learning.  I'm not sure the primary current ring is any serious problem.

I like the scope video.  It clearly shows the voltage needed to get enough feedback to start oscillation.

[zytra]

Agreed. I did the same calculation (and got the same result) in post #88 - I wasn't 100% sure of the result mainly because of the discrepancy on the peak to peak current. I can't explain why I am seeing twice as much as the estimation from the equations. But the calculated 15 kHz would not match if the 24 uH estimated inductance wasn't correct. If it is, then how can the reactance calculation be off... I'm a bit puzzled on this one. I'll connect the primary to the LCR meter to verify that value of 24 uH. edit: the LCR reads 23.2 uH; close enough.


I'm also about to double the DC blocking capacitor value to ensure that it has a direct impact on that low frequency ring.

And yes, at this point I am just trying to learn as much from these tests.

edit: I added a 4.7uF in parallel of the 4.7 uF DC blocking cap. The low frequency ring decreased in frequency as we expected. I find those "modulated" rings difficult to measure.

Primary Inductance: 23.2 uH (measured)
Resonance Frequency (system): 104,600 Hz (measured)
Reactance: 15.25 ohm
Current Peak to Peak: 21.64 A (calculated)
Current Peak to Peak: >40A (measured) - *** I think I should be looking at the "max" and not the peak to peak on the oscilloscope, though, if so the calculated and measured data would agree.

Primary Resonance Frequency @ 4.7 uF: 15.26 kHz (calculated)
Primary Resonance Frequency @ 9.4 uF: 10.79 kHz (calculated)

[davekni]

BTW, "modulated" usually refers to lower-frequency changes in frequency or amplitude of the primary frequency, such as the "blob" being amplitude modulation.  This ring is (at least mostly) a lower frequency added to the primary higher-frequency signal.  The added low-frequency signal is hard to pick out for a couple reasons.  One is the "blob" amplitude modulation.  The second is that there is more than one lower frequency present.  The dominant initial one now does appear to be the primary resonance.  It clearly changes as expected with primary cap change.  There is some yet-lower frequency in at least the first plot.  Hard to tell exactly what given the complexity of all these components overlapped.

The initial current peak looks to be about 50A on the scope captures, a bit lower than I calculate.  104kHz is 4.8us per half cycle.  340V * 4.8us / 23.2uH = 70A.  The primary 4.7uF (or 9.4uF) capacitor may have some initial charge.  At least the one side of the bridge output voltage being probed shows an initial offset that would make the initial half-cycle higher voltage.  But, without knowing the initial state of the other bridge output, it could actually start with a lower voltage for the first half-cycle, explaining why only 50A shows up.

Looking at an AC analysis, a square waveform has a fundamental sine-wave frequency component with 1.11x peak voltage (PI/sqrt(), or 340 * 1.11 = 377V peak.  For the full-bridge, output peak-to-peak is twice, so 754V.  At 104.6kHz, 23.2uH has 15.25ohms.  754Vpp / 15.25ohms = 49App.  That isn't far from what you are scoping, except for the "blob" where higher secondary current is adding more load.

Not sure where during the burst the final zoomed-in scope capture is.  One feature is quite different than any previous such captures.  The bridge is switching well before current zero-crossing rather than just after.  Notice the lack of a high-frequency noise spike at switching.  That's because there's no diode reverse-recovery snap-off.  The bridge output voltage transition happens as one set of IGBTs turns off, before the opposing ones turn on.

[zytra]

Thanks for the corrections on the current calculations. I used the formula both Kaizer and Loneoceans shared on their SSTC pages but didn't realize they didn't have a full bridge as example. That makes sense though, I kinda figured that out by thinking about how the full positive bus generates the positive current waveform, i.e. ~340V for 0-Max current, and vice verse for the other half.

That final plot was in the part of the waveform where the amplitude is pretty much constant (i.e. a bit past the blob). That was more of a capture to get a measurement of the period to better approximate the reactance off the measured Fres rather than an estimation from JavaTC. I did gather a lot more data and didn't want to abuse of the great help and attention you've been giving  this thread; I also noticed how that one plot shows some deviation from the usually much cleaner sinewaves. This, (and the phase shift) happens relatively brutally around 180-200VDC on the bus, i.e. pretty clean before that. That also somewhat coincides with the phase shift, where under 180VDC current would switch close to 0 current, and it gets increasingly de-phased at higher voltages. A video would have probably been better to get more of a dynamic feel on how that shift and sine deformations are taking place.

[davekni]

By your 2nd plot at ~100Vbus the phase has already shifted to where bridge voltage switches slightly before zero-current, eliminating the high-frequency noise on the Vge waveforms.  I'm not sure why that is different than your reply #82 where the plot at 180Vbus switches after zero-current.  Was primary-to-secondary coupling higher back at reply #82 time?

I have a guess to explain this latest set of waveforms.  At low Vbus, secondary arcs are small, so secondary Q high.  That makes relatively-high secondary current (which is sine-wave), inducing sine-wave current in the primary.  As Vbus rises, arcs increase and secondary Q drops.  That keeps secondary current from rising much as Vbus rises.

The current waveform for the primary without secondary will be a triangle wave (with a bit of rounding due to DC blocking cap).  If you zoom in to the first half-cycle of a burst, current should look more like that linear ramp.  That primary triangle-wave current increases linearly with Vbus.  At high Vbus, that triangle-wave component becomes large compared to the sine-wave current induced by the secondary.

In other words, this latest set of plots look as I would expect. 

[zytra]

yes, that makes sense - for some reason (probably screenshots I've seen from build threads, blogs, etc) I was expecting a sine wave as normal current waveform.

Quite a few things have changed since #82. Not sure if they will explain this though:
- adjusted primary turns (same diameter and wire spacing) turns went from 16 to 11.
- 20 ohm + 1uF were added in parallel of the GDT DC blocking cap
- the resistance across pins 1 and 2 of the inverter was 10k, and was adjusted back to 20k

[davekni]

16 to 11 turns is most likely.  Fewer turns reduces inductance, which increases the triangle-wave current.  Fewer turns also reduces coupling, reducing the sine-wave current.  (Unless the 11 turns is spread out to cover the same length as the 16 turns did - then coupling remains about the same.)

[zytra]

I kept the same wire spacing, so coupling definitely went down as well.