High Voltage Forum
Tesla coils => Solid State Tesla Coils (SSTC) => Topic started by: zytra on December 27, 2020, 04:21:29 AM
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Hi guys,
I've been building my first TC, which initially was going to be powered by a static spark gap.
I steered away from the SG/NST but kept the secondary, which in retrospect isn't a great idea considering SSTC are typically not as long (relative to their diameter).
I went with Loneoceans' SSTC2 circuit. I changed my primary design to a 12AWG wound tightly around the secondary.
The way I got the system working was by disconnecting the secondary feedback and feeding the input of the UCC27425 with a square wave from a signal generator. FYI The rectifier and the AC transformer are both running off an isolating transformer.
With no top load I got the coil to resonate at 299 KHz. With the two large half bowls (stainless steel) mounted, that frequency dropped to 174 KHz.
With roughly 60-65VAC on the output of the variac, discharges were roughly 5-6" long.
As interrupter I am using the second channel of that same signal generator (feeding the base of a transistor that turns an IF optic fiber on and off).
I am not quite sure why the feedback isn't working. I did try to reverse polarity on the feedback. But I haven't checked what the signal looked like on the oscilloscope, yet. I did read a post yesterday that suggested a 1K resistor should be placed before the clamping didoes, but I thought I would try the original circuit before "fixing" it. So I'll probably give this a shot tomorrow.
One question (the main reason I am posting this) though:
I read that TC's without feedback are not running as optimized because the resonant frequency tends to change depending on several factors. On my tests, I didn't seem to observe that behavior off the 10-15 minutes I was playing with it.
However, at some point the nice discharges I was getting (1ms pulses maximum, frequency being varied from 10 to 200 Hz roughly), stopped a heavy plasma came out. Current draw on the wattmeter (on the wall) increased significantly so I turned the variac down and turned off the system. Waited a little bit before turning it back on and it was still outputting plasma rather than discharges. I waited a little more, and after a while it was back to normal.
Can anyone help me understand what that behavior might be? Although I didn't try changing the frequency (as it was definitely outputting something, so it was at least fairly close to resonance), it did feel like something else was at play.
I didn't capture this on video, but if it helps I am sure I can eventually reproduce this tomorrow.
Cheers
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Hi Zytra and welcome to HVF!
Some pictures of your setup would be nice, much easier to help out from images than plain text.
Running a SSTC without feedback is not going to hurt it, as it should be designed for hardswitching in the inverter. I wrote a bit about this and some calculations in the SSTC design guide (https://kaizerpowerelectronics.dk/tesla-coils/sstc-design-guide/).
It sounds like your feedback is too weak or wrong polarity to drive itself. It could also be that the parasitic energy transfer from driving circuit is not enough to kick the coil going in the first place. You need to investigate this further with your oscilloscope.
What you call plasma, I assume that is Continues Wave mode, where it is no longer interrupted, so its running with output at every single cycle of its resonant frequency (or in your case, the frequency you are feeding it with the signal generator)
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Yes, that Loneoceans SSTC 2 circuit has issues with feedback design. The 0.1uF capacitor should be to the right of the diodes (on the CT side). As drawn, it attempts to create DC voltage across the CT. That will distort the feecback waveform and likely saturate the CT core.
Concerning plasma (interruption failing), that is likely some detail of you your signal generator is connected to the driver chip enable pin. Perhaps signal generator amplitude is marginal for disabling the driver. Scoping that path should show the issue.
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Thanks guys.
The "plasma" I experienced is I think consistent with failure in the interrupter. As I mentioned I played with frequency and duty cycle a little bit and increasing the interrupter frequency (at a given duty cycle) tend to make discharges shorter (probably because the pulse length is shorten due to the duty cycle is being kept constant). And the "plasma" looked like what would happen at higher frequency.
I am not sure what caused the (temporary) failure (since it came back after a few minutes with the system off). I initially thought perhaps the signal generator itself was acting up due to RF (and its close proximity, it should have been further away) but in retrospect it would have probably acted up on both channels, hence messing with the resonance frequency I was feeding the driver due to the lack of a working feedback. Another device (too) close was the DC power supply that supplied the small PCB converting the output of the interrupter (signal generator) to fiber optic.
Next time it happens, I'll try to have the scope probing the output of the signal generator to see if anything looks abnormal, if not, then it's likely happening on the driver's end.
Dave, thanks for your comment on the feedback circuit (of the SSTC2). I had seen your comments in at least one other thread and my understanding was that the 1k resistor was the one on the wrong side of the clamping diodes but based on your reply it sounds like it's definitely more about the location of the cap rather than the resistor. Would there be any harm in adding another 0.1uF capacitor on the CT side? If so, that test could be done rather quickly.
Thanks again!
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Yes, it's likely fine to leave the other cap in place. To really make that circuit reliable, there should be bleed resistor(s) to define the initial state of feedback and a bleed resistor on the half-bridge to define it's initial state to the opposite. Then the initial half-cycle at the beginning of an enable pulse will always create a transition on the half-bridge output, with the next half-cycle switching feedback states. Or, as I was describing in another thread, a resistor across the first 74HC74 stage will make it self-oscillating, so that it will start up no matter what the initial state may be. Then bleed resistors aren't needed.
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Thanks Dave, I will add the capacitor before the clamping diodes and add a 1k resistor across pins 1 and 2 of the 74HC14. I'll report back when that's done.
Cheers
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I suggest a larger resistor from pin 1 to 2, more like 10k. That way the feedback signal can take over the self-oscillation reliably.
For best results, reduce the value of the existing 0.1uF capacitor on the HC14 input until the self-oscillation frequency is close to your operating frequency. That will make for faster startup. Something like 1nF instead of 0.1uF and 10k from pin 2 to 1 should get around 100kHz.
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Thanks for the clarification, I'll give this a try shortly!
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Quick update. I did not get to modify the feedback circuit yet. I started where I had left off and decided to see if I could reproduce the interrupter failure. And I spent most of my time trying to figure out why this was happening.
I think the issue relates somehow to the signal generator not being isolated. It should have been if it was only used as interrupter, but since I am using as resonator source the signal generator now shares a ground with the driver circuit. I'll verify this was indeed the cause tomorrow by using a separate signal generator for interrupter and resonator.
I confirm that you guys' guesses were correct. Whenever "it" happens, I was able to verify that the interrupter behavior was erratic - causing a high effective duty cycle on the enable pin - hence loading the system significantly.
More on both topics tomorrow!
Cheers
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Hi guys,
I found an easy way to move the capacitor ahead of the diodes. I used a 3-pin header (I always use 3-pin rather than 2 pin because I feel like they sit better) for the feedback so all I had to do was invert pin 2 and 3 in my plug as luckily the capacitor was across pin 2 and 3 on the PCB. This effectively allowed me to have the capacitor before the clamping diodes. I also had to move the input of the 1k resistor from pin 2 to pin 3. Then added a10k resistor across pins 1 and 2 of the 74HC14. I reinstalled the Schmidt trigger in the DIP socket and that was it, feedback is now working!
Now I'll need to put my hands on one of those UD2.7c so I can use that coil as it was initially intended!
On a side note, using a separate signal generator for interrupter and resonator did not solve the interrupter signal issue. So it was not a ground issue, but simply that the signal generator (or PCB converting the electrical signal into an optical signal) was standing too close to the coil. After testing with 2 separate signal generators for resonator and interrupter, I pulled everything much further away and the issue didn't manifest again.
Thanks again for the help.
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Here's a quick video of the result: https://www.youtube.com/watch?v=wMmnOF0bZLs (https://www.youtube.com/watch?v=wMmnOF0bZLs)
Sorry about the quality, it wasn't great to begin with but after the upload it's quite a bit worse.
Mosfets are running surprising cool.
Before I turn this in a DRSSTC I'll measure Vgs abd Vds, and I'd also like to take some current measurements.
Generally speaking I am trying to keep pulses under 1ms (100 Hz -> 10% max, 10 Hz -> 1% max, and so on). Does that make sense? Is there a method to experimentally estimate what a good maximum pulse duration might be?
Last question, is there a technical reason (besides SSTC being naturally not as challenging on the inverter) for SSTC not to fine tune phase lead and optimize for ZVS?
Sorry for all the questions!
Cheers
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Two limits come to mind for maximum enable pulse width. One is energy stored in the VBus bulk capacitor(s). Unless pulse width is more than half a line power cycle, the energy for that pulse is coming from the bulk capacitor(s). No harm in a long pulse, but performance may not be as expected due to sagging VBus voltage.
The other limit is more critical, the transient thermal capability of the IGBTs or FETs in the H-Bridge. It's also harder to calculate. For an SSTC that is (typically) not running in ZCS mode, switching (switch-off) losses are significant. Switching losses are sometimes listed in data sheets, but must be extrapolated to your operating conditions (current, voltage, gate resistance). Conduction losses can be estimated from on-resistance and RMS current. (For IGBTs, look at the high-current end of the Vce vs. current plot and estimate an on-resistance from that point back to 0. Won't be precise since IGBT V/I curves are not linear.) Add the losses and compare with the spec's transient thermal impedance graph.
It isn't common, but ZCS is possible under certain conditions for SSTCs. It's mentioned in this thread:
https://highvoltageforum.net/index.php?topic=1355.msg10042#msg10042
https://highvoltageforum.net/index.php?topic=1355.msg10073;topicseen#msg10073
Also, my QCW coil is running mostly like an SSTC in ZCS mode:
https://highvoltageforum.net/index.php?topic=1268.msg9330#msg9330
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Thanks for the links.
Agreed, the first limit does not bring any concern of failure if the pulses are a bit long.
For the second one with no idea yet on how much much current is going through the primary, it will be difficult to do any estimation. I do have a thermistor installed to measure Tcase on one of the two IGBT's, and since that second limit relates to thermal impedance, would it be safe to use that temperature sensor to estimate if a pulse duration is acceptable or too high? Or would the sensor, and the user's reaction time would be just too slow to prevent damage in the case of pulse that is too long?
At the bottom right of page 5 of the datasheet ( https://www.onsemi.com/pub/Collateral/HGTG30N60A4D-D.PDF ) there's a total switching loss vs gate resistance for various Ice (which I'd suspect is RMS?). Would I estimate the power losses in W as the switching losses (in mJ) divided by the enable pulse duration? For example, assuming 7 ohm gate resistance and Ice of 15A, the energy loss would be 1E-3 J. Assuming a enable pulse duration of 1ms, the power loss would be 1W. I think I am missing something.
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I managed to hook up the oscilloscope this morning.
Variac set to roughly 15VAC, interrupter settings were 40Hz and 4% duty (1ms pulses).
In yellow I have Vge, and in purple Vce. I am not sure what the high frequency ringing taking place on the collector is, but that doesn't look right.
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A thermistor will be useful to see if your long-term duty cycle is too high and/or heatsinking is insufficient. It will not be useful in determining maximum pulse width. The time constant of heat getting to the thermistor will be seconds, not milliseconds.
For SSTC switching loss, you are interested in Eoff only. Presuming the gate resistors provide sufficient dead-time, the IGBTs should always be turning on with 0Vce, so have no significant turn-on energy. The current to use for Eoff is the current at the time of switching, not RMS. (6.8 ohms may be a bit small to provide sufficient dead-time for TO247 IGBTs. What parts are you using?)
The power during a burst is Eoff * frequency, where frequency is the Tesla coil operating frequency, 174kHz in your case. 1mJ adds 174W during a burst. If conduction losses add another 126W, then total is 300W. Look at the transient thermal impedance graph to see what duty cycle and pulse width would keep temperature reasonable at 300W. 0.3C/W would result in 90C rise at 300W.
The Vce ringing is likely caused by parasitic inductance in the VBus supply (50V here, 340V at full voltage). You may need to add film capacitor(s) across VBus at the IGBTs, from low-side emitter to high-side collector, with short leads. A picture or two of your half-bridge and wiring would be helpful. If you want to minimize parasitic inductance, I suggest using copper planes instead of wires, as in this example I made last month:
https://highvoltageforum.net/index.php?topic=1324.msg9795#msg9795
The ringing may not grow linearly with bus voltage. But 300V peak at 50Vbus is enough to be concerning - may fry IGBTs at higher VBus.
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Thanks David for the clarification on losses.
I put everything on DIY'ed bus bars, but I still have (too many) wires between these bus bars, IGBT's, large bus capacitors. Even the GDT secondary wires are too long. On the next one, I'll definitely do a better job - it was the first time and I really went off the schematics.
My circuit is close to that of the SSTC2 made by Loneoceans. I did add some protection to the IGBT namely a pair of zener diodes in opposition and a TVS diode between gate and emitter (both of those are absent from his design). The 6.8 ohm gate resistor is protected with a schottky diode instead of a regular diode on Loneoceans' circuit.
I also took some current measurements (1V = 1A) on that blue/third channel.
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Quick update, I added a 1uF film capacitor (measured 25 mohm on the LCR @ 150kHz).
I did significantly improve Vce, however, both current and Vge traces seem to be not as good.
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The ring frequency increased due to the lower inductance. Ideally it gets above the switching speed of the IGBTs, so the parasitic frequencies aren't excited.
Looking at your layout, I suggest a couple other relatively-small changes to this build. First, add a short wire under the lead end of the IGBTs joining the center of the half-bridge (collector of lower IGBT to emitter of upper IGBT). That will complete the short current loop through IGBTs and your just-added 1uF capacitor. (Is that capacitor soldered directly to the IGBT leads, not back on the bus bars?) Second, twist together each pair (gate and emitter) of output wires of the GDT all the way up to the IGBT, soldering directly to the IGBTs as close to the package body as is feasible.
Hopefully with those changes, this first built will be robust enough to run for a while.
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Thanks for the tips. I'll give this a shot now.
Yes the film capacitor is soldered on the IGBT leads.
The GDT leads going to the gates are soldered directly on the IGBT as well, however the other ends are going to the bus bar as I find it difficult to do a clean job when soldering multiple wires on one tiny lead. And to be frank, I was mainly thinking it would be easier to swap IGBT in case of failures. But what you say makes sense and I'll do that, with the oscilloscope hooked up it should be easy to make a decent side by side comparison.
Since ringing increased a bit would it make sense to increase the size of the gate resistor?
thanks!
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Yes, I suspect a larger gate resistor would help. Some designs add a smaller resistor in series with the diode (or in series with both the diode and other resistor, so in series with the gate connection). That slows down turn-off a bit, which can also help.
Yes, soldering multiple wires to the IGBTs has down-sides. The parallel-plane layout helps with that, but GDT wiring still needs to connect separately to the IGBTs. The reason for connecting GDT emitter connections directly to the IGBT is that it keeps the high-voltage output ringing (mostly) out of the gate. Part of that ring signal is on the emitter wire from IGBT to bus-bar. That part gets added to gate voltage with the remote GDT return connection.
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I'd like to read more on parallel planes before I start the next one up (DRSSTC, perhaps based on that same 3.5" coil). By parallel do you mean they need be separated by a layer of insulating material? or could they technically be running side by side (co-planar, like a PCB)?
Regarding the capacitor, I changed to a smaller value (0.68uF, with a little higher ESR value 45mohm vs 25mohm) and it seemed like an in-between scenario.
Between cleaner Gate and cleaner Emitter, which one should I pick? Ideally, I'd want both cleaned up of course. The 1uF capacitor did reduce the ripples on the Vbus/Emitter but the gate looked pretty bad, though this ringing is probably faster than the gate can open.
Tomorrow, I could try a film 4.7uF that I have lying around, and perhaps add some resistance to gate if ringing on the gate is really bad.
On somewhat not directly related topic, I tried another coil which I had wound prior to this 3.5" (32AWG). It's 2-3 inches longer, and 4.5" in diameter, but wound with 24AWG. Results were not as good (spark length wise). The inductance on the LCR was a bit lower (only 17mH vs. 27mH on the 3.5" coil). Is that result normal, or could that be symptom of something going on? My basic understanding (not sure if that applies too all types of TC's) is that the spark length (assuming equal voltage among other things) will depend on the ratio of secondary:primary inductance. So starting with a lower inductance value will be difficult to compensate.
With a regular (non-DR) TC, if we want to optimize for spark length, we need to maximize inductance of the secondary and primary to secondary coupling. However, increasing coupling would mean more turns on the primary, hence higher primary inductance which contributes to lowering the inductance ratio. Is there a sweet spot to shoot for when coiling for a non-DR TC?
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For parallel planes, please look back at the link I posted in reply #14. If you still have questions, ask again.
Once GDT output wires are twisted and all soldered directly to IGBT pins, the ringing will not couple much to gate waveforms. It may still look bad depending on how the scope probe is connected. Somewhere here there is a post about instructions for proper scope probing technique. Still, the scope probe and ground lead will have a large loop area for picking up ring signals than properly twisted and connected GDT leads. In other words, connect the GDT well, then focus on reducing the Vce spike voltage.
Concerning maximum spark length, there are many factors. Others here likely know more of what to recommend. You can increase coupling by spacing primary coil turns vertically. That will reduce inductance. Then add a turn or whatever is necessary to get inductance back. Use JavaTC to test options before bothering to try them. Stretching the primary higher does increase the risk of arcing from secondary to primary.
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Thank you. Now that I have the GDT wires twisted and soldered on the IGBT themselves I'll focus on Vce. Actually based on your post, I think things are looking pretty good, I was only concerned about the degradation of the gate on the scope but that could very well be that I had to move the probes when I soldered the cap/moved the wires and that now the probes are picking up junk. Vce looked a lot better since the cap was added. Twisting the GDT wires and soldering them to the IGBT didn't help or at least not as significantly as adding the cap did.
The only you recommended I haven't done yet was adding a short line between the high side emitter to the low side collector. That's a bit more invasive and I'll need to more access to do that. Also, when I think about it, current is (should) never flowing from the high side emitter to the low side collector, so what makes this still a good thing to do?
I took a second look at your low parasitic inductance how-to post. At first I thought you were mainly describing a way of building a bridge for those without access to copper clad, bus bar and the like. But after that second read, I'm just realizing how clever the 2-horizontal, 2-vertical layout/arrangement is! My comment/question on polarity was answered on its own: I was worried about the induced capacitance created by 2 plane conductors separated by an insulator, but with your arrangement the positive and negative are always side by side rather than facing each other separated by insulator. I think I will rebuild my half bridge tomorrow following your technique, I'll have to cut part of my heatsink to make it fit in the enclosure. The only drawback is that it makes for a crowded gate pin.
The SSTC2 Half bridge circuit has only 2 (large) capacitors and they're part of the doubler circuit. In my build both of these caps are connected to the bus bar but through a pair of 6" wires. They're just too big to make that connection shorter and still fit in a decent size enclosure. The issue is that they're part of the doubler circuit and their center tap is also the connection to the primary coil, so if I was to add two fast film capacitor on my new "2 by 2" half bridge, would that be ok? I am attaching a schematic of what I suggesting:
- have both primary coil connection from the "2 by 2" half bridge (like yours)
- keep the 2 large electrolytic capacitor that are part of the doubler
- add 2 film capacitors (one on the high side, and one on the low side)
My question is do I need to keep a line connecting the center taps of the 2 electrolytic caps and the 2 new film caps?
Note: I added (some of) the modifications I made to the original circuit so far thanks to your help:
- moved the cap on the other side of the clamping diodes
- added a 10k resistor across the first inverter channel
- added a 1uF film capacitor across Vbus directly soldered on the IGBT's leads
- not shown, but I have 2 opposing zener diodes and a TVS diode across gate and emitter on both IGBT's
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Twisting GDT wires directly to the IGBTs is primarily to protect the gates from transients that could damage the IGBTs (punch through gate oxide due to excess voltage). It isn't surprising that there wasn't any obvious change in scoped signals. (For FETs, clean twisted-pair gate wiring is more critical. FETs are often fast enough to react to the gate spikes, causing multiple high-frequency output transitions.)
Two reasons for a low-inductance connection between low-side collector and high-side emitter. First, momentary conduction between the two IGBTs does occur when voltage lags current phase, as in the one plot you posted that included current. When the low-side IGBT turns on, the high side IGBT is off. However, current is flowing through the high-side diode within the IGBT package. The diode draws a spike of current as it turns off (stored minority-carrier charge). As that current spike ends, voltage on the low-side IGBT spikes up due to wiring inductance between the two. Same happens when the high-side IGBT turns on. (I have one H-Bridge using IGBTs with relatively-slow diodes. Even with my 2x2 layout, just the IGBT lead inductance makes problematic spikes.)
The other reason: With phase-lead and proper dead-time, no current flows through both IGBTs simultaneously. However, current does rapidly switch from flowing through one IGBT to flowing through the other IGBT. Whichever IGBT is turning off will see a voltage spike due to the inductance to the other IGBT. If the two IGBTs are tightly coupled, then the other IGBT's diode clamps the voltage.
There is no need to connect the two capacitor center-taps. Another option is to return the primary coil to the bulk-cap center tap. Then you can use a single film capacitor across VBus (and eliminate the plane split on one side of the 2x2). That adds a bit of wiring inductance in series with the primary coil. No fast current switching there, so no problem. BTW, multiple smaller caps in parallel will further lower inductance compared to a single larger film cap. When I rebuilt that 2x2 example into a full-bridge, I added eight 10nF 630V C0G ceramic caps between VBus+ and VBus- bridging the plane split. That made switching spikes even lower.
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Thanks Dave.
With the 2x2 layout, I'll have, like you, 2 capacitors almost on the IGBT's leads. I won't wire the center tap of these 2 caps to the large bulk ones if not needed. If you have any tip on sizing the 2 caps on the 2x2 feel free to share - I know they need to have the lowest ESR possible but capacity wise I'm not sure. When those 2 are added, do I still need the one you suggested I add (across Vbus).
With that layout the high-side emitter and low-side collector will be naturally connected.
I did play with JavaTC a little bit to see how the number of turns on the primary impact coupling and primary inductance. I had 7 turns yesterday, the peak current measured yesterday didn't exactly match the number calculated off the reactance and half bus voltage though. I think the energy transfer doesn't apply to SSTC but I still plotted it just in case.
But as expected, increasing the number of turns does increase primary inductance, reactance and coupling.
I then tried reducing the number of turns to 6, 5 and 4 and couldn't obviously much of a change in the overall behavior or arc length. I actually wouldn't be able to say which of 4, 5, 6 or 7 turns did better, arc length wise. With the help of the oscilloscope I could probably identify which one had the highest peak current though. I didn't test all the way up to full bus voltage either, so these tests are probably not ideal.
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I was suggesting you could add one across VBus instead of the other two. Then it becomes 1x2 (1 plane for half-bridge output on one side and two planes for VBus+ and VBus- on the other side). That might make it small enough to avoid cutting your heatsink? Works if your coil returns to the center of the bulk caps.
If you use the 2x2 version with two caps and return the primary coil to that center tap (and don't connect to the bulk center tap), then you can eliminate the 4.7uF cap that is in series with the primary coil. These two caps will serve that purpose too. Something around 4.7uF should be fine for these two caps. Might get away with smaller ones down to 1uF depending on how much current you will be running. Larger doesn't hurt.
I have seen a couple DRSSTC builds here that by bad luck had the local H-Bridge film capacitors resonate with the wire inductance back to the bulk caps at 1x or 2x operating frequency. That is problematic, as it causes high VBus voltage swings. Not knowing your wiring inductance, I can't say what exact value to avoid. Just scope VBus at the bridge to make sure there isn't a large AC signal.
At your ~160kHz frequency, angular frequency (2*PI*F) is roughly 1MHz. Thus two 1uF caps in series would be 0.5uF or 2 ohms reactance across VBus. If VBus wires were very long (high impedance) from bulk caps, then 50A would make 100V ripple. The wires are likely short enough to be under 2 ohms reactance at operating frequency. If wire reactance were also exactly 2 ohms, that is the problematic resonance that I'd mentioned. (Or if they were both 1 ohm at 2*F.)
Yes, I think JavaTC is aimed at spark-gap coils. Still quite useful for inductances, coupling, and resonant frequency estimation.
In general I'd go for the most primary turns that doesn't hurt performance. That will reduce primary current, so reduce IGBT heating and all the voltage spikes that are caused by current switching. If you want to use a more quantitative measure of performance, measure secondary current. Add a small resistor in series with the secondary, or in series with the ground lead of the feedback CT. Scope voltage across that resistor.
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I'll stick with you 2x2 as is. The only thing I might not need to keep is the 330 uF cap (that's across Vbus) considering the 2 bulk capacitors are not far away. I'll have to check but I don't think I have a lot of >350V capacitors in this size.
The heatsink is way oversized anyway (I was experimenting with slayer exciters prior to starting this build and I killed a bunch of mosfets). I realized after getting the SSTC up and running that the interrupter significantly reduces the stress on the mosfet, and with moderate duty cycle, they don't get hot at all. I am not looking for high duty/continuous operations. So scaling the heatsink down shouldn't be a problem. I'll get keep the fan in the enclosure to circulate and perhaps use smaller heatsinks on both IGBT's, I am keeping the thermistor so I'll have an eye on the temperature anyway.
I played a bit more with primary turns, and increased it all the way to about 15 turns. 7 will remain a good number a turns as I experienced secondary/primary arcs with as little as 10 turns without even pushing the variac more than half way. 15 turns yielded discharges on primary with only 30-35VAC.
I'll try to turn this coil into a DRSSTC next week, just need to build the driver.
Edit: Added some pics of the 2x2 layout I'm working on. It's actually using 1" wide copper (1/16" thick), 4 strips all 2.25" long. That makes for 2.25x2.25 footprint. The insulation later is 1/8" G10 I had lying around. Overall it's 2.25x2.25x0.25 - a bit overkill but that's what I had around me.
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Looks great, but that thick copper is going to make soldering very difficult. It will sink heat away from the iron faster than the iron can supply it. Might need a micro-torch. The 1/4" total thickness will require more IGBT lead bending, but that is a minor issue compared to soldering.
If you do fit an electrolytic on the 2x2, that should prevent any issues of resonance with wiring inductance. Larger capacitance will lower resonant frequency and impedance, and the cap's ESR will damp whatever resonance might have still been there.
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I had to solder components to 1/8" copper bus bar a while back (twice the thickness) and didn't have too much problem, so hopefully it will be the case here too. I'm working on the new layout in the enclosure and I think I should be able to fit an electrolytic directly on the 2x2.
I might be even able to just re-layout the rectifier/doubler and have the 2 large bulk capacitor bolted on the bus bar which would simplify things a lot.
Thanks!
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I piggybacked on your 2x2 concept and came up with an interesting idea to significantly simplify my particular configuration.
Basically I was trying to implement the copper/G10 concept to the rectifier and was trying to "attach" it to the 2x2 I made this afternoon. Then I realized that it would be a lot simpler to make the 2x2 longer and slightly wider to add one copper trace, this way everything would be on a single board.
I've sketched up the idea off a screenshot of my CAD. I think with this idea I could probably keep the DC blocking cap (and most of the original circuit), and perhaps just keep the 1uF I added across +/- Vbus.
What do you think?
Edit: Modeled it quick and dirty in CAD
Edit: was able to decrease the size substantially by relocating the bulk capacitors
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Yes, that is great! Your 3D views are helpful for visualization. It's looking like laminated-copper structures used on commercial power systems.
I do suggest extending the copper shapes to cover as much area as possible. In other words, minimize gap widths except for what is needed for voltage withstand. The gaps between copper are where magnetic field lines sneak through, creating parasitic inductance. Of course, exactly as drawn is still way better than wires.
The point of my example is overlapping copper planes with minimal gaps (especially minimal gaps that overlap gaps in the other layer). The overlapping planes can be bent into 3D shapes to accommodate mechanical requirements. I've seen a couple coil builds that have a 90 degree bend with overlapping copper planes for bulk caps mounted horizontally.
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Thank you, yes, I can easily reduce the gap between two adjacent buses.
In this particular case, the enclosure was designed/printed to fit the caps vertically, so I don't need to put them parallel to the board and as such they'll have the closest path to the buses possible.
I'll try to build that today, and even perhaps test it!
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I got the board done, and it's ready for assembly.
I found 1/32" copper and 1/16" G10, so it's a bit thinner than the one from yesterday
I need to figure out a plan for the gate line resistor/diode and the gate/drain protection tvs/zener.
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Looks good.
For gate circuitry, I usually make a small board (dremel-tool cut copper-clad usually) that extends roughly vertically or angled back over the IGBT bodies. Gate leads bend back to solder to that board, as do separate emitter wires. Usually easiest to solder the emitter wires onto the IBGTs close to the package before attaching to the 2x2 power board. My second post of that 2x2 example shows this, where I turned it into a full-bridge.
Not being mechanically-skilled, my gate boards usually have no support other than the gate and emitter leads. (I use somewhat heavy wire for the emitter connection just for rigidity, not because it carries much current.) You will likely be more clever.
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Happy new year!
I split and trimmed my original PCB. Its layout was actually pretty decent for what I wanted to do.
I pulled a couple pins and replaced them (upside down) with 90D headers which gave me the support I was looking for on the opposite side of the IGBT gate pin.
I tinned the 2x2+1 board and added the 2 diodes and the wires from the AC and those to the coil. I kept the DC blocking cap in this configuration and I'll figure something out for the heatsink later. I'll add the bleed resistor directly across the capacitor screws.
I wanted to try it today so I went ahead and hooked up a signal generator on the input (removed the inverter first) but couldn't get anything out of the driver. Probing the input shows no problem, however probing the enable pin shows nothing is happening there. I think the issue is the phototransistor, or the transistor that's feeding the enable pin. Not a big fan of the IF-E91A/IF-D92 combo, my PCB is a bit crowded and couldn't find a hold-down screw. Anyway that shouldn't be too difficult to fix.
Can't wait to see how much cleaner this layout will be on the scope.
Cheers
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Looking great!
I've had good success with IF-D92 at 660nm. Haven't used the IF-E91A (930nm) emitter. PMMA fiber has lower attenuation at 660nm. I've used PLT133/T6A for transmission as well as 660nm 5mm LEDs. Newer LEDs are much more efficient. Drilling a hole in the end of a 5mm LED and gluing the end of a fiber into it couples much more light than PLT133/T6A or any of the other transmitters I've seen.
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I pulled the driver out of the enclosure and powered it outside and everything looked good. I'm guessing perhaps the fiber had moved and wasn't properly aligned (the plastic cap around the phototransistor can move up and down). I received some ST type emitter/receiver (those used in the UD2.7), so I'll probably upgrade to those soon once I figure out the direction I'll be heading for the DR "upgrade".
Anyway I was able to verify polarity of the GDT, and then proceeded with some tests. Had to flip the feedback, and that was it.
The attached screenshots show were taken at various bus voltage as I was increasing the output of the variac.
1. I could immediately see the benefits of this parallel plane layout. This is without the extra bus cap that helped cleaned things up a few days ago.
2. Other than for the last screenshot (110VAC), everything looks really good. That last screenshot has some "waves" which I can't really explain. Note that the cyan line is a current probe (clamp) so I think it's fully isolated from the other 2 channels (grounded to the emitter of the high side IGBT).
3. What perhaps struck me the most is the current values. If you scroll a few posts up you'll see the values I was measuring and I was getting over 30A p2p at roughly 60V on the bus. On that last screenshot today, I'm at less than 10A p2p at over 300V on the bus. I'll double check everything but that seems rather odd!
edit: On a side note I was giving some thought if that 2x2+1 layout could be upgraded to a full bridge without adding too much complexity. And I think I found an elegant way to do just that. Basically, on my top view image with the colors (black, red, cyan, orange, green), all I would need to do is to invert the positions of the green and orange strips. By havin the green strip "alone" in the center, the orange strip would be properly located for edge mounting of additional IGBT's.
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The 2x2 design works quite well for full-bridges. I've made many full-bridges and only a couple half-bridges. In a later reply to the example I'd posted I convert it to full-bridge. (No voltage-doubling incorporated directly, so it's just 2x2 without an extra center strip. Your center-strip version should work well too.)
Definitely something odd about the current. It doesn't rise proportional with voltage - possible if arc loading is increasing at high voltage/current. Also odd that a new relatively-low ring frequency shows up only at higher voltage. There are often issues with high-frequency high-voltage on the scope ground even with a floating scope. I'd suggest scoping the low-side gate and collector with ground on the low-side emitter rather than high-side.
The previous high current at 60V also seems a bit odd unless the primary was in resonance (ie. small value for the "4.7uF" cap in series with the primary). Could be possible with a high-Q secondary and high coupling. But that still leaves the question as to why it changed.
Are you measuring current with a commercial clamp-on current probe? If so, is it good to 160kHz and high-enough current?
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Yes, your second posts showed the full bridge upgrade which pushed me to think of a way around to get the other 2 transistors to fit on the opposite side of the first 2.
According to JavaTC my coupling is probably between 0.30 and 0.35 or so.
The current probe is a cheap one but with decent reviews, it should be alright at my resonance frequency: https://www.banggood.com/Micsig-ACDC-Current-Probe-CP2100A-800KHz-10A-Maximum-Measurable-Current-100Apk-70_7Arms-DCACpk-p-1625010.html?rmmds=myorder&cur_warehouse=USA It's rated for 10A/100A and I've got it set to 100A.
I haven't even pulled it out of the system since the measurements a couple days ago.
I'll probe the low side IGBT and move the ground clip to the low side emitter.
If there was any resonance taking place on the primary wouldn't we see other obvious signs on the Vce trace?
edit: on the full bridge question, yes I didn't realize that the doubler would need to be dropped unless I found some much higher voltage IGBT.
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That current probe looks fine. Are you sure your scope scale is set correctly? It outputs 10mV/A on the 100A setting. If the scope is set to 5V/div for a 10x probe (as I think it shows in the images), that's 500mV/div or 50A/div. Then your current is hitting 80App at 340Vbus.
Changing from half-bridge to full-bridge doesn't change the required IGBT voltage rating. It does double output voltage, which will double current for a given load impedance. I've just never happened to integrate voltage doubling with a bridge, preferring to keep the "high" frequency stuff separate from the line-frequency circuitry. Also allows reuse of power supplies (voltage doubler or other) among projects.
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Duh me, well double duh.
1. Of course. With a full bridge each IGBT still sees half the bus voltage.
2. You're right, screenshot from a couple days ago shows the correct scaling ratio of 100:1, where as today, for some reason it defaulted out to 10:1. Had to reboot the scope the yesterday, maybe the settings didn't get saved properly. That makes more sense.
edit: Going off the idea of a full bridge and the 2-diode rectification, I drafted another one with full wave rectification. I'll double check tomorrow, but I think I need an extra trace for AC stuff, which will be more of a 4x2 layout. This still uses the doubler. Not 100% positive but it could also make sense to add a couple of MKP capacitors across the Vbus +/-. Even though the 2 large electrolytic capacitors are right there I think these would help, if I can fit them that is.
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Each IGBT sees full bus voltage, same for both half and full bridges. When one IGBT is on (roughly 0V), the other IGBT in that leg sees full bus voltage.
I still wonder about that 1.4MHz ring showing up at higher voltages but not at lower. I have no idea if it is a problem or not. Were you getting arcs during that test?
Not quite sure what schematic you are implementing with that 4-diode layout. It looks like a voltage doubler with added diodes across the caps (which should never conduct, so not be of use).
Yes, some film caps are still a good idea. Electrolytics tend to have higher impedance at high frequency. I've recently started adding SMD ceramic caps across the gap between VBus+ and VBus- (630V C0G/NP0 dielectric 10nF, but will buy some 33nF ones shortly). Their very-low inductance reduces the highest-frequency ringing where even film capacitor lead inductance is significant.
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First let me thank you again for your continuous help with all this, I've learned a lot!
Let me clarify that my question regarding Half Vs Full bridge was about my case (using a doubler, with the SSTC2 as base schematics). In this schematics, a half bridge is used. So, when the high side IGBT's gate is open (the low side one is closed) the current flows from the 339V to the center tap of the doubler, which should be 170V or so. Is this incorrect?
By going to a full bridge, although each IGBT would also see the same 170V, the primary coil would actually see the full bus voltage (339V).
It could be that what I call "bus voltage" is not accurate. Or maybe I am still missing something.
I've attached a screenshot, with channel 1 on high side gate, channel 2 on low side gate, ground is on the low side emitter, and channel 3 is the (now corrected in scale) current probe on the primary.
As far for the schematics, I haven't double checked it yet, but it's based on the Quasar60 plans I had bought a while back, which uses a full bridge. Their power supply uses a full wave rectifier and a doubler. I'm attaching a screenshot. Those plans are for a DRSSTC but it doesn't matter I'm only looking at combining the power supply and the full bridge.
Regarding the high frequency ring, I don't know. Could that be relate to the ground clip picking up something? That seems to happen on every rising/falling edge of the gates. The fact it gets through the IGBT (since it's showing up on the current trace), suggests the IGBT is able to open and close that fast? Which is why I was thinking it might just be the ground clip picking up something. But to answer your questions, yes, all the screenshots were taken with the live coil releasing arcs.
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The IGBTs see 339V for both half and full bridge. The primary coil sees +-170V in the half bridge and +-339V in the full bridge. Consider the half bridge. There is 339V (Vbus) from low-side emitter to high-side collector. When one IGBT is on (0V), the other has 339V. Look at your IGBT voltage waveforms to see that.
The ring may have been related to connecting the scope "ground" to the high-side emitter. I suggest retesting with the scope ground on the low-side emitter (VBus-), measuring low-side gate and collector voltages. Another possibility is the changing arc load at higher voltage somehow excites a 1.4MHz resonance somewhere.
Yes, that circuit has two unused diodes in the bridge. Was likely copied from a schematic that had a jumper between the bridge and caps. That was common for supplies designed for both 120V and 240V options. (Less common now that most supplies have PFC input stages.) If you are always running on 120V into a doubler, there is no use for the other two diodes.
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Thank you, that makes sense - I had no problem visualizing what the primary "sees" in half bridge vs. full bridge, and probably assumed the IGBT was seeing the same thing.
I should have mentioned that it would be good to eventually test it on split phase, which I suspect would need the extra 2 diodes. It's not for right now, and I would have to consider the specs of the components. I was actually wondering it (split phase) is not that frequently done, but maybe it's just a matter of transistor specifications.
I have finished another coil, slightly bigger, so I'll give it a shot and see if it changes anything on this ringing.
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I have installed the bigger coil (quite a bit higher inductance, at 75 mH versus 47 mH with the original coil) as I really wanted to get an additional reference point.
The primary uses the same wire (12AWG) and 7 turns or so (same number of turns as before).
The system is substantially more power hungry. I am pulling as much (if not more) current as I was at a fraction of the bus voltage. For the first time I can also see the IGBT temperature go up.
Interesting observations
* On the waveform of the current, it takes quite a bit more time for the current to "ramp up"
* I couldn't understand why "nothing" was happening with my usual 1ms pulse
* but it makes as you can see it takes more than 1ms for the current to go up (and create discharges)
Considering the secondary as a lower resonant frequency and that I kept the same 4.7uF would it be possible that I have an unintentional DR?
I doubt it because after plugging numbers into JavaTC the primary is still much lower than that of the secondary.
Attached screenshots show:
* yellow: Low side gate (ground clip on low side emitter)
* purple: Low side collector
* cyan: primary current
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I spaced the primary further away from the secondary and added more turns.
Current is a bit more manageable in a sense where I got to around 150V on the bus for current around 80A.
In terms of spark length I don't think it would be any better even if I was able to raise the bus to 330V. I might be able to as the current didn't seem to increase (much past a certain voltage, like before).
edit: by the way, I meant to ask this before and another reason why I wanted to test a second coil. Am I just "lucky" that it seems like switching it taking place at close to 0 current?
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Looks like nice progress. Yes, with arcs forming it is normal for current to not increase linearly with voltage as the larger arc lowers secondary Q.
The long initial delay is because the driver is oscillating at a higher frequency for a long time before locking in to the secondary frequency. It may be that the feedback input HC14 chip has low hysteresis so that the 10k feedback resistor I'd suggest you add is causing high-frequency oscillation rather than at or below resonance as intended. You could increase the 10k value, perhaps to 20k. Or, you could add a small capacitor from HC14 input (pin 1) to ground to lower the initial oscillation frequency, perhaps 100pF or so. (The long initial high-frequency oscillation may be causing most of your driver and IGBT power dissipation.)
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That long delay at the beginning of each pulse (screenshots 38, 39), were resolved by playing with the primary. I tried lowering turns initially on a primary tightly wrapped around the secondary. That didn't help, actually, it made it quite a bit worse. Increasing the number of turns seemed to help although I could "hear" some action taking place somewhere between primary and secondary.
My solution was to space the primary a little bit and add some turns. I stopped there but I'm pretty sure I could add some more turns and still improve. Once that was done, arcs seem a little longer (maybe 13-14" up from 11-12") which. Current seemed a little bit higher but this is probably something to expect with a larger coil.
It sounds like this fits your theory, somehow. Perhaps the higher coupling resulted in a different feedback waveform causing that high frequency ringing to be more manageable?
I would really like to be able to address that high frequency ring, especially if it helps with efficiency.
Not sure if you saw my edit, is the switching taking place close to current zero crossing just pure luck? I guess the value of the DC blocking cap would be one way to play with phase if adjustments were needed?
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As uspring pointed out, close to ZCS requires high coupling and high secondary Q. The relatively-slow current increase after the frequency locks does suggest high secondary Q. I'm guessing that your zoomed-in scope plots are late in the burst when current is close to maximum. You may be less close to ZCS early in the burst, which could also be slowing the ramp a bit.
The initial high-frequency oscillation before frequency locks is (probably) unrelated to the 1.4MHz ring in some previous scope plots. Don't see any of the 1.4MHz now, so am guessing it was caused b scope "ground" connected to half-bridge output.
The initial 1.3ms of high-frequency before current ramps up is dissipating power charging and discharging gates and IGBT output capacitance. I can't tell what frequency that region is without a zoomed-in capture. My favorite driver technique is to have it self-oscillate close to resonant frequency without feedback. PLL drivers do that, but those are relatively uncommon. A weakly self-oscillating circuit that is overdriven by feedback is simpler, and what the 10k is intended to do. However, it looks like frequency is too high. Raising to 20k will lower frequency way down, as it will be based on 10k and the 0.1uF capacitor between CT and diodes. That may be OK, as one transition may be enough to start oscillation. To adjust frequency, either add a small capacitor in series with the 1k resistor and change the 10k to 20k (or larger to tweak frequency down), or add a capacitor from HC14-1 to ground (and perhaps lower the 10k resistor value). Either one should work. (Or drop the 1k to 470 instead of increasing 10k to 20k.)
Most drivers w/o self-oscillation work fine. However, the first bridge transition must make enough feedback signal to cause the next transition. This requires the bridge's initial state to be different than the initial gate waveform drives it, which requires some bleed resistors to define initial state. (Or luck in where leakage currents leave the initial state.)
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I was re-reading the PLL SSTC thread from earlier this month with upspring's comments which is what reminded me to ask about ZCS. Sadly though, the quality factor is not something I can make a lot of sense of yet.
That being said you are correct, the zoomed in traces are taken after the initial burst, when the current maximum waveform was taking place (I was keeping a close eye on those).
I will implement one of your two suggestions tomorrow. But just to clarify the goal would be to address the high frequency ring showing up on all traces twice per period, right? I've highlighted them in the attached screenshot.
Also, I need to space the primary a bit more and add some turns. After looking in more details at the inductance and coupling values in JavaTC it looks like pushing the primary inductance without increasing the coupling (which I tend to keep around 0.30 or so) is what gave me the best results, so I'll try pushing it a bit further and see what's the impact on current and spark length.
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My suggested change has nothing to do with those spikes. They are caused by switching slightly after current zero-crossing. The IGBT turning off is in diode-conduction. When the opposing IGBT turns on, it forces the diode off. The diode's reverse recovery current causes that ring.
Rather, my suggested change is to address the 1.3ms of oscillation before current starts to ramp up. I can't tell from the zoomed-out scope plots just what frequency that is. It looks to be well higher than resonant.
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Ahhh. Sorry for the confusion!
I no longer have that long (over 1ms) period where the current was very small. This was fixed by spacing out the primary further and adding turns. I can't reproduce that without redoing the primary. I plan on working on the primary further so maybe I'll encounter that scenario again if so I'll make sure to take screenshots.
I did move my setup away from the desk and encountered some difficulties with the IR diodes again. I followed your advice and used a red LED instead. I first tested by holding by hand making sure the phototransistor was sensing the signal. It sure did. I didn't have any 5mm LED so I used a 3mm, and instead of drilling the LED, I drilled a 3mm hole in the body of the IR LED from IF. That works great, and was able to extend the length of the optical connection.
As far as your suggestion, I did add a 10K pot in series with the 10K that was there. I figured I would have a little bit more flexibility.
I will do two tests with the pot @ 0 (i.e. 10K total) and another one with the pot @ 10K (20K total), and scope the first few microsecond of a pulse.
edit: tests done
screenshots 52, 53, 54 are with 20K across pins 1 and 2 of the SN7414 inverter
screenshots 55, 56, 57 are with only 10K
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Something rather strange happened after the previous set of tests, i.e. shortly I moved the coil away from the desk.
Since the beginning being short on differential probes, I had both the variac and the small 110-12VAC transformer on an isolation transformer. Although I didn't change anything to that part of the setup, shortly after finishing the tests reported in the previous post, I blew a rectification diode (low side, which is where the oscilloscope ground clip was connected) in the middle of a test (70A or so on the primary). I replaced the diode and started investigating, as it turns out, the oscilloscope was the problem. The only thing that had changed was the outlet I was using for the isolation transformer. I tried putting the oscilloscope together with the rest of the stuff on the isolation transformer (I had never tried that), it didn't help. I tried putting the oscilloscope on another isolation transformer and same result.
Anyway, I removed the passive probes and used the one differential probe for the gate, I have another one the way.
screenshots 52 through 55, are the new larger primary (15mm of gap between it and the secondary) and 18 turns.
screenshots 56 through 59, only 16 turns.
The latter gave better sparks overall, and it starts "Cracking" at a lower voltage. Current draw is roughly the same (although the second set of screenshots have 2 turns less, the actual length of the wire is same as I didn't cut it, the extra 2 turns were left loose for now).
I'm not clear as to why the current trace more ringing than it did earlier today.
I'll keep playing the primary turns some more, I'm not sure I can do any better than the primary I had yesterday.
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Sounds like either your isolation transformer has an internal fault or there's some connection to line ground in the bridge circuitry that I'm not aware of. Normally running the bridge VBus supply from an isolation transformer allows grounding VBus- with a scope probe. Wherever the issue is (isolation transformer or other ground path), that may explain some previous anomalies too.
The low-frequency current ring is likely at the resonant frequency of the 4.7uF cap and the primary inductance. Adding a bleed resistor across the 4.7uF cap should help. (The unwanted initial 1.3ms of high-frequency oscillation may have centered half-bridge voltage, so avoided that low-frequency ring. Adding a bleed resistor across the 4.7uF cap is a better solution. Although I do wonder what would cause that cap to charge between bursts. Scoping the half-bridge output will show if it is going to one rail or the other after a burst. Ideally it would remain at half of VBus. That's what the bleed resistor should force, presuming it's only small leakage current pulling the output high or low. It is also possible that one IGBT is partially damaged, causing high leakage current. Perhaps the scope ground issue damaged one IGBT a little.
Since you happen to be switching slightly after zero-current point, fewer primary turns may move that switching earlier. I think after-zero-current is unusual for SSTCs, but don't have much personal experience. My SSTC is unusual (ferrite transformer instead of primary winding), so not useful as a reference point.
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It's the same isolation transformer I have been using, so it should rule out it being defective. Though, as I read your message, I may accidentally inverted phase and neutral when I reinstalled the driver after adding the 10K pot this morning. The following two tests were low power where I wanted to see the impact of the added 10K. I then blew the diode (and the variac fuse as an immediate consequence, forgot to mentioned) when I raised the voltage as I was getting ready to play with primary turns.
I should be paying more attention to Phase/Neutral in general, and I think this is the perfect example as to why I should.
Edit: follow up question though, in the event of rectified split-phase (through a 220V isolation transformer), would you be able to use a scope to probe Vbus +/-?
Before I comment on the low-frequency ring, I meant to ask a general/safety question in regards to the testing environment. I have a steel cart, which I thought would be practical to put the coil on top, driver/bridge on the mid shelf, and oscilloscope on the bottom shelf. I would wire the steel cart to my RF ground of course. Is that a good idea? My idea behind this was that it would protect everything from possible discharges, although with the current spark length I am dealing with it's rather unlikely.
I am still not clear what you call low-frequency ring. Are you talking about the waves on the first hundred microseconds of each pulse (on those last screenshots, I was doing 10Hz, 1% duty, or 1ms pulses)? With that 6" primary and 15-20 turns, the primary resonance is between 9 and 12kHz. That seems to match the roughly 100 us period of those waves.
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If the isolation transformer is working properly, the output is floating. There is no difference between phase and neutral, so it makes no difference which way it is wired. To me, seeing a difference with phase/neutral swapping is more evidence of a faulty isolation transformer.
It should make little difference in circuit operation even without an isolation transformer as long as no scope (or other) grounds are connected to the bridge circuitry. It is convenient to have neutral at the doubler center-tap. Neutral is roughly at ground potential. Don't connect scope ground to neutral (unless isolated), but you can still scope bridge circuitry without connecting the ground clip. With neutral on the doubler center-tap, you can connect the scope ground through a ~0.1uF capacitor to neutral for better high-frequency probing.
The cart has advantages and disadvantages. The cart layers reduce possible magnetic or capacitive coupling between circuits. If connected to line safety ground, it reduces issues of shock from touching the cart and some other grounded equipment. It protects from discharges as you mentioned. (Most DRSSTC designs have a not-quite-closed ground loop outside the primary as a strike rail. Most SSTCs don't include that as arcs usually aren't long enough to pose a risk.)
The primary and secondary coils need to be spaced above the cart to allow a path for magnetic field at the coil bottoms.
However, when debugging live circuits, a large grounded structure (cart) can increase shock risk. If you accidentally touch a live node such as VBus+ etc. while otherwise insulated (shoes on sitting on and sitting on a plastic chair), there's no shock. If you were also grabbing the cart to steady it and/or you, then the cart completes the shock circuit.
Yes, it is exactly that 9-12kHz ring I'm referring to. At 10Hz, it would require 4.7 mA to charge the 4.7uF cap to 100V between bursts. That is high for leakage current. It may be worth measuring half-bridge output voltage with the driver off (no gate signals). If at VBus+, try pulling it down with a power resistor, say 10k-100k, to see if it goes close to 0V. If at VBus-, try pulling it up with a power resistor. Without gate drive, it should easily go to whichever rail you are pulling it. If not, then one of the IGBTs or TVS diodes (if you have them) must be faulty. (Or pull it with a resistor to doubler center-tap to measure what current is being drawn high or low.)
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Thanks, I'll stick a wood top for now :)
I remember I failed to tell you that I forgot to add the bulk capacitor bleed resistors I originally had on the bridge when I rebuilt it a couple days ago. It's been a bit of pain (I hate keeping capacitors charged) to discharge them manually during all these tests today. I'll add them back tomorrow, but I doubt they have anything to do with that low frequency ring, I already had that with the old bridge. I'll definitely add a bleed resistor on the DC blocking cap as well, what value/power should I use for this one?
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As you suspect, bulk-cap bleed resistors will have no effect on operational performance.
I was going to suggest a resistor value for across the 4.7uF cap, but realized that there must be excess (at least a few mA) leakage current to build up significant voltage between bursts. It would take a lower value higher power resistor to overcome high leakage current. And I don't know how high the leakage is. So it is likely better to first figure out where leakage current is coming from.
On the other hand, one easy way to measure leakage current is to add a resistor across the 4.7uF cap and then measure voltage while not driven. If leakage current is low, a 10k resistor would dissipate little power. If leakage current is high, the resistor could see half bus voltage (170V) for ~3W power dissipation. If you have a 3+W 10k resistor, that would work well. Or, use a lower-power one and test quickly before it gets too hot.
The resistor value isn't critical. 100k would work fine if leakage current is low. Lower than 10k is fine too. Power needs to be high only to handle faults or high (faulty) leakage currents.
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I have a 10W 20k that could work.
Would the (bleed) resistor alter the capacitor function of DC blocking?
For that measurement, the differential probe across the capacitor is all that is needed? One trace while the coil is in operation and some more shortly after? Or did you mean to simply use a voltmeter across? It's a rather small capacitor so it shouldn't take too long to discharge it. The much larger (almost a 1000 times) bulk capacitor take a minute or two to discharge with that same 20k resistor.
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That 20k will draw <1mA during normal operation, totally insignificant compared to 40A or whatever flowing through the 4.7uF cap. Negligible effect on DC blocking. (If the driver is accurately enough 50% duty cycle, it would run without a DC blocking capacitor.)
A differential probe measurement would work, but I was just thinking of a voltmeter. Power up the bridge and not the driver and measure DC voltage. Ideally it will be close to zero (low leakage current into 20k resistor). That would be good, but leave me puzzled as to why so much 10kHz ring.
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At full bus voltage (330VDC), with the driver off, I am measuring basically 0 across the resistor (see attachment).
I've then run the coil at roughly half that bus voltage (50VAC or so) and recorder a short video - the voltage seems to be under 1V, if you feel it's needed I can repeat that test at full bus voltage and with the scope attached in place of the voltmeter.
https://www.youtube.com/watch?v=_96_QEaFj88&feature=youtu.be (https://www.youtube.com/watch?v=_96_QEaFj88&feature=youtu.be)
edit: is there a reason why that 10Hz seems to be less visible (perhaps even not present) toward the end of the pulse? It's very obvious at the very beginning of the pulse, and still very apparent through the higher current portion of the pulse but after that it's fairly dim if there at all.
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I'd thought that the 10kHz ring was due to initial charge on the 4.7uF capacitor. Clearly it is not due to that. So anything I say about why it exists and why it decays away is only speculation.
Because the primary current always starts with a positive half-cycle (of the normal 170kHz frequency), there is a little bit of energy at 10kHz. I don't think that is enough to explain what you are seeing.
The only other possibility that comes to mind is of primary current is coupling into the secondary current feedback CT. Is that CT next to any primary wiring?
Or, possibly there's a resonance at the same ~10kHz of the secondary feedback CT and the 0.1uF DC-blocking capacitor between it and the diodes. That seems unlikely, but you could try increasing the 0.1 uF to something larger and see if the ring frequency drops or amplitude reduces.
Anyone else with more SSTC experience know if this level of blocking-capacitor/primary coil resonance is typical?
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The number of primary turns affects primary inductance, which affects the primary resonance. On some of my earlier tests with that 4.5" secondary, where it required super long pulse to get the coil going made those low frequency rings more difficult to see.
The secondary CT is a few inches away from the wires going to the primary.
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A few inches should be plenty presuming the CT uses a ferrite core.
Yes, I remember that the slow-start plots had little ring. That should perhaps be some clue to the puzzle, but I can't think what that implies at the moment.
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Hopefully playing with the primary yields some more hints.
I am circling back to my full bridge layout questions, I continue reading and found cobaugh's thread which lead me to his website where all his specs were listed. Would I need a 4-diode bridge rectifier if the system was designed to be compatible with 240V split phase? Cobaugh is in the US as far as I know and since he mentioned 240V I suspect he is talking about split phase. However, he's using a 2-diode power rectifier. Unless he is using for something else? https://labs.cobaugh.io/hv/tesla/dr81/
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The design you linked is voltage-doubling 240Vac to get 680Vdc. It's exactly the same circuit as your doubler, just with parts rated for the higher voltage.
I'm also in US (Oregon). My Marx generator and DRSSTC use 240Vac from a 40A cloths-dryer outlet (or 208Vac 30A three-phase when I'm at the local science museum). Although the 240Vac is split-phase, neutral is not used. (Unlike the above link, my system starts with a crude PFC stage.)
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Thanks, I understand the doubler part of the circuit, I am just wondering about the rectification. A few days ago you mentioned that the schematics I had put together had 2 extra diodes. Your message suggested (I might have misinterpreted) that the 2 extra diodes could have been used in a circuit with split phase, which uses 2 hots that are 180-degree apart, no neutral. Like most heavy domestic appliances in the states, dryers, welder, ovens.
But looking at what cobaugh did, it looks like he may have only 2 diodes like my current circuit, which would means the extra 2 diodes in typical bridge rectifiers are not needed on split phase either.
These 4 diode rectifiers are used everywhere though which is why I was surprised by your comment. I knew it was possible to rectify with 2 diodes and thought the other 2 made the rectifier more efficient by not "wasting" anything. But considering these 4 diodes are this common I am just wondering why manufacturers aren't saving on 2 diodes if they can?
edit: here's what I am referring to: https://www.quora.com/There-are-two-different-methods-of-full-wave-rectification-One-has-two-diodes-and-other-has-4-diodes-Which-is-better-Give-reasons-why (https://www.quora.com/There-are-two-different-methods-of-full-wave-rectification-One-has-two-diodes-and-other-has-4-diodes-Which-is-better-Give-reasons-why)
I am not seeing the distinction between them mainly because both can be (are) used on the domestic 110VAC. The schematics with the center tap transformer shows 3 wires coming out of the transformer and diodes rectifying the 2 halves, but on most TC schematics using 2 diodes only show line and neutral.
edit2: I guess I should expand my thoughts a little bit more about the next project. One of things I am debating about is where or not I should (like this SSTC) have both the bridge and the rectification taking place in the same place (i.e. under the the coil); or if I should separate the power supply from the bridge. The latter was my plan as I was more or less planning to follow the quasar60 plans I had. But then doing that 2x2+1 layout for the SSTC showed me how compact it can be. I am still leaning toward the separate power supply which I can equip with ammeters and voltmeters to get readings without needing to be too close. If so the plan would be to design the full bridge for a maximum Vbus of 680 or so when ran on 240VAC, although it will run off 120VAC 95+% of the time.
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Try simulating all the variations. There are several free analog simulators, both on-line and downloadable. My favorite is LTSpice - use it for home and work.
It all depends on what voltage you want. If you are after 170V, then 4 diodes on 120V or 2 diodes on 240 split-phase. If you want 340V, then two diodes on 120V (voltage doubler) or 4 diodes on 240V. If you want 680V, then 2 diodes on 240V (voltage doubler again). Of course, there's half-wave too.
The two-diode split-phase circuit is almost always with local transformers, not with split-phase line power. With line power, split-phase makes even lower power factor on each phase.
Local or separate VBus DC supply is all your preference for packaging. Personally I like separate for large projects. I use the same 450Vdc 10kW PFC supply for two projects, and likely more in the future.
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I need to try LTSpice, heard a lot of good things. I've used circuitlabs which has a GUI I like but I am not happy with the simulation tool.
I'll put together a full bridge of the same IGBT's for the SSTC. I am doing all this mostly to learn and experiment in I've always been drawn to, and I really like understanding how the various components and property work together. So testing the same coil with a full bridge is something I'd like to see before moving on to DR. I'll do a similar 3x2 layout as I did for the half bridge, and if I'm not mistaken with a full bridge the DC blocking capacitor is no longer needed. It'll be nice to see if there has been any change on the low frequency ring as well.
Edit: Actually I should be able to modify the one I build a few days ago. Just need to invert the N / L strips so that the other half bridge is on the edge rather than in the center, I'll do this in the morning :D
I forgot to post this: https://www.youtube.com/watch?v=JZnPGhCBrik&feature=youtu.be (https://www.youtube.com/watch?v=JZnPGhCBrik&feature=youtu.be) this is pretty much the best I could do so far, let's see if the full bridge improves this a little.
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DC blocking is no more or less needed with a full bridge than with a voltage-doubled half bridge. For half-bridge SSTC designs that don't have a center rail for VBus, a blocking capacitor is absolutely needed. For a full bridge, and for your half-bridge with a center voltage rail, DC blocking is needed only to handle driver duty cycle variation away from 50%. That variation is almost always enough to make DC blocking wise.
Have fun with LTSpice! Learning is the point of experimenting for most of us.
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I took the half bridge apart and started modifying into a full bridge (and keep the doubler) but then realized this is probably not going to work as I am short of a transversal trace on my 2x3 layout. So tomorrow I'll put together a new board, it's good practice anyway.
I've attached a quick draft of what I wanted to do, the red cross shows the trace that I can't keep moving to a full bridge, and why I need to redo my layout.
I've made an extra 2 small gate PCB's. Though I think I might reduce the resistor value from 6.8 ohm to perhaps half that considering the one GDT/driver is supplying 2 additional gates. I took a look at the gates with the scope and they looked a bit slower than with the half bridge.
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Be careful about reducing gate resistance. It provides dead-time during switching, not just edge slew rate control. IGBTs generally turn on faster than turn off (due to stored minority carrier charge). The diode keeps turn-off fast while the resistor slows turn-on. If the full bridge is slowing gate waveforms, it is most likely slowing both, not increasing dead-time. Rather than reducing gate resistance, I'd focus on reducing GDT and wiring leakage inductance.
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That makes sense, I'll stick with those values then. I made a new GDT, and in retrospect I think I should have reduced the number of turns a little bit. I'll test it as is though, because the gates "looking" slow on the scope probably doesn't mean a lot, it will be better to evaluate this quantitatively when the coil is running.
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So... I managed to mess up my layout and of course, I only realized that when checking everything after all components had been laid out on the freshly CNC'ed 5oz clad. haha. I need to find a good PCB software. Making those with Solidworks is far from ideal even though they're overall very simple.
Oh well there's always tomorrow.
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You have a very clean and low inductance layout. Regarding GDT construction I think you should take a look at the excellent practical guide from thedatastream (can only be found on archive.org now) https://web.archive.org/web/20200120153028/http://thedatastream.4hv.org/gdt_index.htm and if you want to change the gate resistor values, this is a super nice and simple guide to follow with a oscilloscope: http://www.richieburnett.co.uk/temp/gdt/gdt2.html
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Thanks Mads, I'll study the GDT in more details tomorrow and compare today's screenshots to those with the half bridge to see if there is room for improvement.
Dave, do you have any thread or website that talks about your PFC power supply?
I kept the same primary, but I know I will to adjust it considering the higher voltage across it.
I removed the 4.7uF DC blocking capacitor. I still have the voltage doubler. And of course other than for the full bridge, everything else is the same. I kept the 6.8 ohm gate resistor like I had with the half bridge. In fact, I kept the schottky, zener and TVS exactly as it was, leaving only a different GDT (with twice as many secondaries).
My observations so far:
- Arcs seem better, I'll have to play with it more to be sure. No significant difference, though. At least not with the same primary.
- The high frequency stuff seems quite a bit more present
- The switching seems to be a little soft than before
- The low frequency ring is still there, weirdly. Although not as pronounced in the couple tests I had time to do. Not sure what to make of it since the 4.7uF cap is gone.
On the scope screenshots I have top/bottom left IGBT's on channels 1 and 2.
High side collector/emitter on channel 3.
Primary current on channel 4.
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Regarding the low frequency ring, it's still there and depending on the bus voltage, it's more or less visible.
Here are 6 screenshots of the current waveform starting from 30VAC all the way to 105VAC (15VAC increments). And all of them have that same odd ~10KHz-ish in them.
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First, it looks like the DC blocking capacitor is needed. The gate-drive duty cycle is not close enough to 50% to get away without one. Many of the scope captures show the current settling out to not centered around 0. Depending on how low frequencies your CT passes, the real current may be much farther off. The next-to-last capture shows Vge waveforms getting confused, likely by the current offset, which then resets the current DC component closer to zero. One of the IGBTs may be coming out of Vce saturation due to the excess current, which generates huge power dissipation spikes in the IGBT.
The high-frequency noise through most of each half-cycle is likely coupling from the secondary arc into probe leads. I wouldn't worry much about that. The ring spike on Vge waveforms during switching is likely IGBT diode snap-off since switching is occurring after zero-current. Not likely to be problematic given your nice low-inductance bridge layout now.
The low-voltage plots show Vge ringing after a burst ends at close to the same frequency as the initial current ring. That suggests that the ring may be due to the 1uF DC blocking capacitor in series with the GDT primary. Try adding damping parts across that capacitor as in the UD2.7 schematic, say a series 1uF + ~20 ohms in parallel with the existing 1uF. That will likely fix the low-frequency ringing. (Still a remote chance it is the feedback CT resonating with the 0.1uF capacitor, but GDT seems more likely now.)
Your GDT looks good from what I can see. May not need as many turns for your operating frequency. If reducing turns, the ~20 ohm damping resistor suggested above will be optimum at a lower value. With fewer turns the GDT can handle more DC current, so damping may be possible with just a resistor alone across the 1uF DC blocking capacitor in series with GDT primary. (I use 2 or 3-turn GDTs on large cores with no DC blocking capacitor. I always have DC blocking on bridge output.)
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Thank you, Dave.
Bridge DC blocking cap: I noticed the current waveform wasn't centered, and even double checked that the current probe had been zero'ed properly. I'll add it in the morning. DRSSTC always have the MMC in series with the primary anyway, I wanted to see if removing it took care of the low frequency ring.
Thanks for the advice on the GDT DC blocking cap. I didn't know it was possible to run without one with two drivers with opposing outputs through a GDT. I'll try adding a resistor/cap in parallel of the existing cap. I went a little hard on the number of turns exceeding what I had on the half bridge GDT. I'll prepare another one. I actually followed your suggestion of using cat 5 (1 wire of each pair in parallel as primary, and the other wire of each pair as secondaries) and that was pretty easy, compared to my first GDT where I used one twisted pair of cat5 that I ran through a 1/8" copper braid. It was nice and thin but a pain to run that twisted pair through the braid. One thing that's not great on that circuit is that it uses 12V input, so the GDT uses a ratio of 1:1.5 to raise the gate voltage to ~18V.
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I'd forgotten about the 1.5:1 GDT ratio directly from a driver chip. That explains why Vge waveforms have slower transitions with full-bridge load on the driver chip.
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I meant to post this one before and forgot. It's with nothing on the bus, i.e. what I suspect is the resistor across pins 1 and 2 of the inverter, to initiate an oscillation. I was thinking about this last night and I remembered how the oscillations looked comparable to the low frequency ring.
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And here are a few (same waveforms with different time scales) with the bridge DC blocking cap added.
It did fix the symmetry on the current waveform. And it also seems like it's crossing to be switching quote a bit softer too (especially on rising current).
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I think that no-bus-voltage plot shows the resonance is GDT with blocking capacitor. The oscillation frequency of the 20k resistor and feedback 0.1uF capacitor is too low to show even a half-cycle during that scope capture. (The 20k still serves a purpose, keeping the feedback voltage near the HC14 threshold.) Adding the R+C damping across the 1uF GDT input DC blocking capacitor should reduce that ring to a half-cycle or so.
The other traces all look fine. Vge transitions are on the slow side, but probably OK. Not much that can be done without changing to a UD2.7 or similar driver with higher current and voltage GDT drive capability.
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Yes, the gates traces aren't as steep as they were with the half bridge. It won't hurt, but perhaps affects performance a little bit. I spent some time gathering data for various numbers of primary turns. Nothing really conclusive, I'll post about it later after I look at the numbers in more details.
By the way I didn't mention but that nothing on the bus screen capture triggered off the end of a pulse (i.e. when the enable pin of the driver goes low). It does oscillate for a while.
As opposed to the same capture but this time captured off a rising pulse (when the enable pin goes high, see attached screenshot where we can see both oscillations at the beginning of the pulse and at the end). Weirdly enough, it doesn't oscillate for nearly as long.
Tomorrow, I'll add the RC damping you mentioned.
edit: I just remembered, I had the same waveform on the scope (when nothing was on the Vbus) with the half bridge and more importantly with the previous GDT. Although, it's not impossible that both GDT's would resonate with the DC blocking cap at roughly the same frequency, how likely would that be though?
Also, looking how that low frequency ring affects the shape of the current waveform, how likely is it that it affects performance?
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That GDT resonant frequency depends on GDT primary inductance and the 1uF DC blocking capacitor. If the GDT cores were similar and the primary turns-count similar, then the frequencies will be close.
The GDT ring at the end has little energy to excite it, just the final half-cycle of normal oscillation. At the beginning with no bus voltage, it has a full 12V step for a long period compared to the oscillation cycle.
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I've meant to gather data at various primary turns for a few days and finally got around to doing it today.
- Measuring arc length wasn't easy and should be pretty much be ignored, and I can't even objectively say that there was any difference in length. I had a ruler against the wall behind, and stood as far as I could to minimize parallax. Then I would wait a little for arcs to discharge along the length of the ruler. Yeah, not the best protocol but I wasn't looking for accurate length either.
- I also measured current draw at the wall, PF and power. No calculations here, just readings off a cheap wattmeter.
- All tests were done with 110VAC to the rectifier/doubler, 10Hz and 1ms pulses.
I started from 20 turns and then went down 2 turns at a time. It's only when I got to very low number of turns that I thought about checking the P2P current in those pulses, to realize they were significantly higher. I quickly wrote down that value for 6 turns, repeated the test for 20 turns, put those down as notes in the table.
I was a bit surprised that although the primary current was significantly higher for 6 turns, it wasn't higher at the wall at all. Considering the power draw was so small overall I think most of current draw at the wall basically are losses, with very little actually going into an arc. I could measure what's actually going in the primary by pulling the RMS current since we know the bus voltage; this way I could compare.
After those tests, I set the number of turns to 11, at least for now.
edit: sorry posts crossed. Thanks, we'll know for sure tomorrow once I had damping! Thanks
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Higher primary current without higher wall current suggests that primary current and voltage are farther out-of-phase with 6 turns. Can't tell at that zoom level. Since performance is similar, 20 turns is much easier on the bridge.
I like your quantitative characterization of performance. Measuring secondary coil current may provide a more repeatable indication of coil performance for optimization. It is also useful to compare secondary current phase with primary voltage phase. If too far off, performance will suffer. Your after-zero-current switching is (I think) uncommon for SSTCs, and may indicate mismatched phasing of primary voltage with secondary current.
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I may be a bit too cautious, but I'm trying not to kill the coil or at least maximize time between repairs so I can gather as much data as possible to hopefully make sense of the physics behind all this. But I think my 1% duty cycle is just too little, that is for the tests I ran today. I am trying to not push more than 1ms pulses (which is what I deducted as a safe pulse duration from the IGBT datasheet). And since experimentally 10 Hz, 1% (1ms) gives me the longest arcs (rather, the best ratio of arc length over power consumed), they became my go-to tests parameters.
My secondary system is probably a little bit on the high side in terms of impedance (60kHz). By the way, running longer pulses is something I've tried for quick tests and they do help a lot, making arcs thicker and deeper. They appear longer but not sure if they actually are or if they just appear that way being so much brighter.
I've put the current probe on the secondary a few days ago just to have a look, I'll do that again and correlate that to primary voltage. I do wonder if this phasing is dependent on spark load.
One thing that has been consistent throughout all the tests so far is the shape of the current pulses. Aside from that low frequency ring, regardless of the enable parameters (frequency/on time) I always get that "blob" that's usually right in the middle of the low frequency ring. The shape of the blob will vary slightly based on the bus voltage (and as seen today, by the primary turns). What is causing the current waveform to have a stronger P2P in that early region of the pulse? I understand why it takes some time for the current waveform to get a certain regime (i.e. the feedback loop to lock on the resonance frequency), but then why does it drop/stabilize lower? Spark load will affect the resonant frequency but the feedback is there for that. And it can't possibly be capacitors discharging considering the energy stored and the fact that it does stabilize for the rest of the pulse, a cap discharging wouldn't - the time scale of those pulses (1ms) is a fraction of the mains' period.
Edit: I calculated an inductance of 24 uH for the primary as it currently is now. At 117 kHz (measured from screen 90) it should yield a reactance of 17.5 ohm, which at 320VDC should mean a peak to peak current of 18.5A or so. I measured (screen94) ~40A peak to peak away from the initial blob... I'll check my probe - seems like a big discrepancy if we consider the 40A - but on that screenshot the blob peaked over double that value. That same primary, with the 4.7uF DC blocking cap has a resonant frequency of just under 15 kHz, which incidentally still matches the low frequency ring. I'll have to measure it more accurately. Maybe I'll try a more tightly coupled primary again. You said the GDT might resonate with the driver's DC blocking cap, how would that cause the primary current to react that way, the primary circuit would need to resonate with that as well, wouldn't it?
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Spice simulations can provide great insight to what's happening. It can be tricky to know what details need to be modeled.
I expect the initial higher-primary-current "blob" is caused by high-Q secondary resonance and associated (induced) high secondary current. As the arc grows, it adds capacitance, but also resistance in series with that capacitance, which reduces Q. Lower Q drops secondary current, which reduces induced primary current. It is that induced current from the secondary that allows primary current to rise well above what it would be with no secondary in place.
My guess is that the arc stops growing when current settles after the blob. The arc likely reaches an equilibrium, dissipating as much power as it is being fed. It might be interesting to try shorter (perhaps 0.5ms) enable pulses at a higher repetition rate.
For simulating the arc, it is easiest to run separate simulations for different arc lengths, with different resistances and capacitances. It is possible to model changing resistance and capacitance. I've done that for my DRSSTC, but don't have accurate information on how resistances and capacitances change as a function of voltage and time.
Concerning GDT resonance showing up on primary current, I think it is related to the relatively-slow slopes on Vge waveforms due to driver chip output impedance. As GDT current rings, it will pull Vge duty cycle higher and lower. If the primary coil and blocking capacitor happen to resonate at the same frequency, that will amplify the current ring. Simulation would show if that is likely as long as driver output impedance and GDT inductance and coupling factor (leakage inductance) are modeled. Adding GDT DC blocking capacitor damping will also verify if this is the cause of primary current ring.
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Thanks Dave, I have started playing with LTSpice. I'm sure it will be a great tool once I am more familiar with it.
Your explanation on the "blob" makes sense; I'll now test the damping theory for the GDT DC blocking.
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The 20 ohm + 1 uF in series of the existing 1 uF DC blocking cap on the GDT didn't help, in fact it looks like the waveform hasn't changed, and the low frequency ring is still there.
I've made a short video which will show a bit more how that current waveform evolves from 0VAC to 110VAC: https://www.youtube.com/watch?v=_LIvVoRE4zg&feature=youtu.be (https://www.youtube.com/watch?v=_LIvVoRE4zg&feature=youtu.be)
here's the current state of performance: https://www.youtube.com/watch?v=GMmQSiZCmdc&feature=youtu.be (https://www.youtube.com/watch?v=GMmQSiZCmdc&feature=youtu.be)
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It is clear that at least by now the GDT resonance isn't a significant factor in primary current ring. Looking back, it was clear in your reply#86 too. The primary ring is dominantly ~12kHz. The GDT ring was ~5.5kHz before, and ~4kHz now (as expected with the added cap and resistor). Looking back at older plots, primary current ring has some lower-frequency components, which might have been GDT related. Now there is little 4kHz visible. (At 4kHz, 1uF is ~40 ohms, so perhaps the series resistor would be better around 40 ohms instead of 20.)
24uH primary with 4.7uF DC blocking would resonate at 15kHz. So that is likely a factor in the latest ring plots, at least magnifying any other ring-inducing factor. Not being a DRSSTC, I can't think of any beat frequencies that would cause the ring. You could try adding damping to the 0.1uF. Perhaps another 0.1uF in series with ~200 ohms. And/or, you could test changes and/or damping on the 4.7uF primary DC blocking capacitor. Much of this would be aimed at experimenting/learning. I'm not sure the primary current ring is any serious problem.
I like the scope video. It clearly shows the voltage needed to get enough feedback to start oscillation.
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Agreed. I did the same calculation (and got the same result) in post #88 - I wasn't 100% sure of the result mainly because of the discrepancy on the peak to peak current. I can't explain why I am seeing twice as much as the estimation from the equations. But the calculated 15 kHz would not match if the 24 uH estimated inductance wasn't correct. If it is, then how can the reactance calculation be off... I'm a bit puzzled on this one. I'll connect the primary to the LCR meter to verify that value of 24 uH. edit: the LCR reads 23.2 uH; close enough.
I'm also about to double the DC blocking capacitor value to ensure that it has a direct impact on that low frequency ring.
And yes, at this point I am just trying to learn as much from these tests.
edit: I added a 4.7uF in parallel of the 4.7 uF DC blocking cap. The low frequency ring decreased in frequency as we expected. I find those "modulated" rings difficult to measure.
Primary Inductance: 23.2 uH (measured)
Resonance Frequency (system): 104,600 Hz (measured)
Reactance: 15.25 ohm
Current Peak to Peak: 21.64 A (calculated)
Current Peak to Peak: >40A (measured) - *** I think I should be looking at the "max" and not the peak to peak on the oscilloscope, though, if so the calculated and measured data would agree.
Primary Resonance Frequency @ 4.7 uF: 15.26 kHz (calculated)
Primary Resonance Frequency @ 9.4 uF: 10.79 kHz (calculated)
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BTW, "modulated" usually refers to lower-frequency changes in frequency or amplitude of the primary frequency, such as the "blob" being amplitude modulation. This ring is (at least mostly) a lower frequency added to the primary higher-frequency signal. The added low-frequency signal is hard to pick out for a couple reasons. One is the "blob" amplitude modulation. The second is that there is more than one lower frequency present. The dominant initial one now does appear to be the primary resonance. It clearly changes as expected with primary cap change. There is some yet-lower frequency in at least the first plot. Hard to tell exactly what given the complexity of all these components overlapped.
The initial current peak looks to be about 50A on the scope captures, a bit lower than I calculate. 104kHz is 4.8us per half cycle. 340V * 4.8us / 23.2uH = 70A. The primary 4.7uF (or 9.4uF) capacitor may have some initial charge. At least the one side of the bridge output voltage being probed shows an initial offset that would make the initial half-cycle higher voltage. But, without knowing the initial state of the other bridge output, it could actually start with a lower voltage for the first half-cycle, explaining why only 50A shows up.
Looking at an AC analysis, a square waveform has a fundamental sine-wave frequency component with 1.11x peak voltage (PI/sqrt(8)), or 340 * 1.11 = 377V peak. For the full-bridge, output peak-to-peak is twice, so 754V. At 104.6kHz, 23.2uH has 15.25ohms. 754Vpp / 15.25ohms = 49App. That isn't far from what you are scoping, except for the "blob" where higher secondary current is adding more load.
Not sure where during the burst the final zoomed-in scope capture is. One feature is quite different than any previous such captures. The bridge is switching well before current zero-crossing rather than just after. Notice the lack of a high-frequency noise spike at switching. That's because there's no diode reverse-recovery snap-off. The bridge output voltage transition happens as one set of IGBTs turns off, before the opposing ones turn on.
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Thanks for the corrections on the current calculations. I used the formula both Kaizer and Loneoceans shared on their SSTC pages but didn't realize they didn't have a full bridge as example. That makes sense though, I kinda figured that out by thinking about how the full positive bus generates the positive current waveform, i.e. ~340V for 0-Max current, and vice verse for the other half.
That final plot was in the part of the waveform where the amplitude is pretty much constant (i.e. a bit past the blob). That was more of a capture to get a measurement of the period to better approximate the reactance off the measured Fres rather than an estimation from JavaTC. I did gather a lot more data and didn't want to abuse of the great help and attention you've been giving this thread; I also noticed how that one plot shows some deviation from the usually much cleaner sinewaves. This, (and the phase shift) happens relatively brutally around 180-200VDC on the bus, i.e. pretty clean before that. That also somewhat coincides with the phase shift, where under 180VDC current would switch close to 0 current, and it gets increasingly de-phased at higher voltages. A video would have probably been better to get more of a dynamic feel on how that shift and sine deformations are taking place.
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By your 2nd plot at ~100Vbus the phase has already shifted to where bridge voltage switches slightly before zero-current, eliminating the high-frequency noise on the Vge waveforms. I'm not sure why that is different than your reply #82 where the plot at 180Vbus switches after zero-current. Was primary-to-secondary coupling higher back at reply #82 time?
I have a guess to explain this latest set of waveforms. At low Vbus, secondary arcs are small, so secondary Q high. That makes relatively-high secondary current (which is sine-wave), inducing sine-wave current in the primary. As Vbus rises, arcs increase and secondary Q drops. That keeps secondary current from rising much as Vbus rises.
The current waveform for the primary without secondary will be a triangle wave (with a bit of rounding due to DC blocking cap). If you zoom in to the first half-cycle of a burst, current should look more like that linear ramp. That primary triangle-wave current increases linearly with Vbus. At high Vbus, that triangle-wave component becomes large compared to the sine-wave current induced by the secondary.
In other words, this latest set of plots look as I would expect.
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yes, that makes sense - for some reason (probably screenshots I've seen from build threads, blogs, etc) I was expecting a sine wave as normal current waveform.
Quite a few things have changed since #82. Not sure if they will explain this though:
- adjusted primary turns (same diameter and wire spacing) turns went from 16 to 11.
- 20 ohm + 1uF were added in parallel of the GDT DC blocking cap
- the resistance across pins 1 and 2 of the inverter was 10k, and was adjusted back to 20k
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16 to 11 turns is most likely. Fewer turns reduces inductance, which increases the triangle-wave current. Fewer turns also reduces coupling, reducing the sine-wave current. (Unless the 11 turns is spread out to cover the same length as the 16 turns did - then coupling remains about the same.)
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I kept the same wire spacing, so coupling definitely went down as well.
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As expected. It is nice when the world starts to make sense.
I've learned quite a bit from this long thread, especially with all your detailed scope measurements. I hadn't realized how significant induced sine-wave primary current was compared to the triangle component of a primary alone for normal SSTC designs. (My only personal SSTC experience is unconventional. H-Bridge through ferrite-core transformer generates +-4kV square wave fed to bottom of secondary. No primary winding.)
BTW, way back you'd asked about my PFC. No, I haven't documented it. No one would want to copy. As typical for me, most of the analog circuitry is implemented with discrete transistors rather than ICs.
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Thanks, I'm a bit surprised but happy you were able to learn some!
Everything makes a lot more sense now; I'll continue experimenting with primary turns (coupling/inductance) I have a feeling this part of the system has room for improvement. I'll convert this into a double resonance shortly as well, I have almost everything built just to put it all together.
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I'll post some stuff soon in a thread about the DR that I am putting together reusing this full bridge initially.
Meanwhile, I wanted to do an experiment with this bridge and driver. I didn't want to create a new thread for this especially as it's directly related to the stuff built in this thread. Basically I turned a multi-chamber secondary structure out of PTFE and got around to wind it today. I initially hooked it up to one of those ZVS boards with underwhelming results. It's a possibility that my primary didn't have enough turn (I went with 2x 2.5 turns - the driver is designed for a center tap primary). Anyway, I thought I'd give a shot on my SSTC driver/bridge. So I disconnected the 7414 and feedback, and taped my signal generator to the input pin of the driver chip. Results were quite a bit better than with the ZVS driver. And since I still had the oscilloscope hooked up the same way it was for the SSTC I immediately saw the IGBT were hard switching. With very little input power my temperature probe already showed they were heating more than they do with the SSTC at much great input power. I tried adding the DC blocking cap again thinking it might move the phase a bit, and it did but nothing significant. First screenshot is without the 4.7uF and the second is with it.
Anyway I stopped there and started doing some research on the topic and found that Steve Ward actually did something very similar: https://www.stevehv.4hv.org/FBD.htm
He doesn't talk about hard/soft switching but other than for a half bridge and a couple of caps it's basically the same concept. He does mention he was able to pull 450W which is probably over 10 times what I was able to pull safely today. IGBT's may not be the best for this, but I was comfortably switching at 150 kHz which is well in the capabilities of those IGBT's. With this soft switching, this project could work. The transformer itself (well the secondary) is a success from what I can tell. I have at least over 3000 turns, everything submerged in mineral oil.
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I'd suggest sweeping frequency at low voltage to find the transformer's secondary resonant frequency. Even with a segmented bobbin, 3000 turns may have enough intra-winding capacitance to resonate well below your 50kHz drive frequency.
More information on your transformer would help too. Roughly what is the cross-sectional area and path length through the core? What is the total gap length between core halves? Or, is it not gapped? (That would explain it not working well with ZVS oscillators.)
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The transformer is fully custom, I'll post pictures later tonight. It's made of 2x "C" shape ferrite bolted together. The secondary is roughly 26mm ID x 50 mm long (that includes 15 separations that are about 2mm thick). The core has an OD of 20mm, meaning 3mm of insulating PTFE. The segmented secondary was turned on a piece of PTFE. The core is not gapped.
For the primary I have 2x 2.5 turns, which is a bit on the small side which could explain the lack of success with the ZVS driver.
After running the transformer on the SSTC driver, I decided to make my own ZVS driver. And since I ended up using roughly the same components, results were the same outside of the capacitor that was film but with high ESR, it ended up heating a lot so I replaced it with a better quality capacitor with significantly lower ESR but also slightly higher capacitance. Results were immediately better, and after playing with the few caps I had available, found that 4.7 uF was giving me the best results. Note: I did go back to the commercial ZVS and put the same 4.7uF cap across the far ends taps of the primary and results were much better, but as good as mine oddly - perhaps due to the other caps still being there. I say "caps" because that driver used 2 for some reason. The ZVS circuit I am familiar with use 1 cap across the far ends of the primary, and this one uses two. I looked at the PCB and it looks like they use 2x ~0.330F but I am not sure how it is all wired together.
I proceeded with assembly of my 200mm plasma ball, flushed it with argon at 1atm and results were great. Voltage was probably a bit high because I can't run a vacuum on that cheap plastic globe (that has a flat bottom - I tried by the way, and it's not a good idea, haha). I used a grounded striker to test contact and it would definitely shock you as opposed to normal plasma ball.
The goal is to make a bigger one (glass, round, under vacuum) so I don't think I will dial down on the voltage yet, just to make sure I have enough for the larger one down the road.
I did experience a set back with a failure of the secondary. The last chamber, last few turns (hard to tell exactly) arc'ed through the PTFE to the ferrite. Not through the thickness which was 3mm but through the last separation which was only 2mm in my design for some reason.
I've made revisions to the design and will turn it this week, increased the thicknesses separating the windings from the ferrite to a total of 4mm. I had to reduce the thickness of chamber to chamber separation to compensate, but I think this will be fine, as I don't expect any arc to get through 1mm PTFE on two adjacent chamber. If it took 16 chambers to go through 2mm or so on the HV side where the potential difference is maximum, I think I should be fine with 1mm between 2 adjacent chamber.
Another setback today after rewinding a spare V1 core. I wound this one with only 2 differences: I didn't fill the last chamber (HV side), and I tried to compensate by adding 1mm more thickness on all of the other chambers. That one failed with an arc within one chamber, along the surface of the PTFE which darkened, but no penetration. I think what happened is that my layering wasn't great on this way, I kinda rushed it last night, the added layers didn't help as it increased the voltage difference within one chamber.
With all tests I found that I was lacking a direct voltage measurement on the HV side. I actually was able to use a HV probe on my early tests (that didn't work well) and measured 8kV. After tweaking the capacitor on my own ZVS I was able to get intense plasma at ambient air and discharges over 2" long, so there is no doubt that my 10kV probe wouldn't be able to work there.
I think I'll copy this in a new thread in the appropriate section because it's pretty interesting too, and some my findings could be of use to someone else.
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It would be interesting to see waveforms for this - primary voltage and secondary with just antenna pickup (reasonable phase, just no amplitude calibration). ZVS drivers usually aren't used with ungapped inductors. Inductance is high and saturation current low. I wonder if your system is running at a frequency determined by leakage inductance and the primary and secondary (intrawinding) capacitance.
Besides the HV end failure, the common tricky problem with segmented bobbins is the wire transition from the top of one segment to the bottom of the next. Unless there are slots or other accommodations in the separation walls, that wire to the bottom ends up adjacent every layer (including the top) of the new segment as it is wound. That leaves a full segment's voltage across two thicknesses of enamel insulation.
BTW, the two 0.33uF (1200Vdc, 630Vac) caps in the commercial ZVS are almost certainly in parallel. They are standard Chinese induction cooktop capacitors, the ones I use for my DRSSTC MMC. Some ZVS units have 6 or 8 in parallel.
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Thanks Dave, I split the thread here and replied there as well: https://highvoltageforum.net/index.php?topic=1391.msg10494#msg10494