SSTC issues (gate signal, interrupter-mode, grounding)

[Max Seiringer]

Hello guys! Thank you all for your help!
I have been working on the coil for a couple of hours again recently, when it dawned on me that i might have used the wrong kind of diodes for the antenna feedback. Totally my fault, this is what you get for not reading the schematics correctly, I guess...I changed them to schottky and now the coil is working! A great moment to finally see some (intended) sparks from this project.
The gate signal looks fine, just a bit ringy. I should probably add some 15V TVS.

However, I have one more question: The circuit is drawing 4 amps at 30VDC at the input and the primary wire is heating up slightly. The mosfets get warm as well, but it's really not that bad. But 4 amps at 30 volts input is way too high, isn't it?

Thanks in advance!
Max

[davekni]

If you plan to run at 230V eventually, then 4A is too high at 30V.

What duty cycle does the enable waveform (555 output) have?  I forget if the driver chip enable issue was fixed.  Running continuously rather than at a low duty cycle would explain high current.

[Max Seiringer]

The 4 amps were measured in CW mode. Now I am running the coil interrupted with a maximum dutycycle of around 20%. At 30V the current decreased to 0,5A.
I even tried to raise the voltage but at 100VAC (approximately 140VDC at the bus) one of the mosfets died silently. The analysis showed a blown gate, this suggests rather high voltage peaks or oscillations at the gate. Is there something to reduce this issue beside using TVS or zener diodes at the gates?
The result of the 140V test was pretty ok in my opinion. Not great but much better than anything I have seen before from this coil, with streamers close to 10cm (4in). Nevertheless, the result should be better at 140V at the bus.

Best regards
Max

[davekni]

Unfortunate that you had a failure already at 140V.  Are you certain the FET failure is just gate?  Does the source-drain still show diode behavior, conducting in one direction and open in the other?  The last scope traces posted show clean Vgs waveforms.

If it is just a gate failure, I'd guess the issue is too much common source inductance (lead length) shared between the high-current output path and gate drive.  Rapid current transitions can induce enough voltage across source lead inductance to disrupt gate voltage.  I'd suggest bringing the twisted GDT leads around the power connections and back across the top of the FETs, soldering to the source leads close to the packages.

Concerning performance to expect (arc length), other members will have better experience.  I suspect that spreading out the primary winding turns a bit increase coupling will help some.

[Max Seiringer]

After checking again you are right! The DS path is basically a dead short, as well as the GS path. Must have been a faulty connection at the first time. What could cause this kind of failure on the lower Mosfet, considering both the upper and the lower one did not even get slightly warm over the duration of the experiment?

Thank you for helping me improving the bridge! The new one already features your suggestions.

Thank you so much for helping!
Best regards,
Max

[davekni]

Power transistor frying (IGBT or FET) is the most common failure with many possible causes.

Looking back at your latest build image, I can't see the bulk cap(s) for Vbus (power to the FET half-bridge, C7 in SSTC1 schematic).  Where is it/they and how long are the wires?  I'd also measure the two polypropylene caps that center-tap Vbus for the return side of the primary winding (C8 and C9).  If one of those failed, that could lead to FET failure.

Once the FET(s) are replaced, I suggest scoping gate and half-bridge output (and the other side of the primary at C8/C9) as the burst (enable pulse) starts and stops.  It's possible that everything looks good during operation, but there's some issue as it starts or stops.

How high a voltage can you supply to Vbus with an isolated supply to allow scoping?  FET (and IGBT) capacitance is a strong function of voltage, lower at high voltage.  The lower capacitance will increase frequency and impedance of the switching ring due to C8/C9/FET wiring inductance.  Even though you made significant improvements there, it's possible that the ring still gets large enough at 140V to cause problems, either with excess Vds or by some parasitic coupling back to gate drive or all the way back to antenna feedback.

If C8/C9/FET wiring inductance is problematic, the best design is using copper planes.  This can be copper foil on a thin insulating sheet or double-sided copper-clad board cut with a knife or dremel tool.  Below are a few links to discussion about this.  These are for full-bridges, but easy to apply to half-bridges.  Use the node for the other half-bridge output as the center node between C8 and C9.
https://highvoltageforum.net/index.php?topic=1114.msg8046#msg8046
https://highvoltageforum.net/index.php?topic=1032.msg7225#msg7225
https://highvoltageforum.net/index.php?topic=1058.msg7685#msg7685
The key to these posts isn't details, but rather the overlapping copper planes, with FETs and caps soldered to the planes with as short leads as possible.  This is how all of my H-Bridges are designed, for Tesla coils and other power projects.

I'm not sure how long your antenna is or where it is placed relative to the coil and driver.  Keeping the antenna away from the driver power circuitry (half-bridge) and/or adding grounded metal shield between the two will help if the issue is extraneous coupling to the antenna.

[Max Seiringer]

Hello!
First off thank you for your help, David! I appreciate it! I gained so much knowledge through your tips and advices you won't believe it.

Secondly, I got myself a brand new four-chanel oscilloscope from Siglent! So no more blurry pictures of my laptop.

To your question about my isolated power supply:
I have a 30V SMPS to supply the bridge isolated from mains. This is currently the maximum voltage that I can measure with my setup. But I just ordered a differential probe, so I can hook the scope up to my variac that can supply up to 270VAC.


To your question about the bus capacitors:
You can see the bulk capacitors together with the rectifier stage in the picture below. I added two extra capacitors directly at the bridge when I rebuilt it yesterday. The two bigger ones at the rectifier are 1000uF each, so 2000uF in total (parallel), and the smaller ones are 680uF each in series so 390 in total. The total capacity of the DC filtering caps is therefore 2390 uF.
As you might also notice from the pictures below I replaced the 0.68uF voltage divider capacitors (C8/C9). Not because they were damaged, just because the new ones are MKP caps that are meant to do this kind of work.



As you suggested, I took some measurements at the lower Mosfet.
In the picture below you can see the gate-source signal (yellow), the drain-source signal (purple) and the secondary signal picked up by a probe sitting nearby (blue). After the gate stops firing, the primary continues to oscillate at the resonant frequency. My guess is that the secondary resonant circuit induces a voltage back into the primary while is rings out.


The pictures below show the gate-source and drain-source voltage in detail.
VGS (yellow) and VDS (purple) at the beginnung of the burst:


VGS (yellow) and VDS (purple) at the middle of the burst:


VGS (yellow) and VDS (purple) at the end of the burst, with the back induced voltage:


I also scoped accross the bridge output. You can see the output signal in the pictures below.
Vprim at the beginning of the burst:


Vprim at the middle of the burst:


Vprim at the end of the burst, with the back induced voltage:


A couple of things to note:
The gate resistors are currently 22 ohm ones. I'll have to change these for lower ones, probably 10 ohm ones. The reason I used them are the Mosfets from the previous bridge (already blown up). The gate capacitance of them was so small I had to use higher value resistors.
With the new Mosfets, the ringing at the bridge output got way worse compared to the output signal of the old bridge.
I use 18V zener diodes in antiseries to clamp the voltage accross the gates.
My Mosfets are always dying at about 120-140VAC input. The FETs die silently and are stonecold. The whole FET is a 0.0 ohm dead short afterwards. This is the main issue, since I would like to go to full 325VDC on the bus for maximum discharge.

Thank you in advance!

Best regards,
Max

[davekni]

Nice detailed scope images!  That's key to understanding issues.

What FETs are you using now?  Many new FETs are optimized for low reverse-transfer (gate-drain) capacitance (Cgd).  This decreases switching times and reduces switching losses.  However, the fast switching causes more overshoot and ringing.  The fast switching can also couple through inter-winding capacitance of the GDT, resulting in high-frequency (MHz) oscillations during switching.  I see hints of that in your Vgs waveforms, and it gets worse at higher voltages.  I've had two projects fry FETs for this high-frequency oscillation issue, using Alpha-Omega-Semiconductor FETs.  (They had some early low-Cgd FETs, which I purchased for the associated low loss.  Then discovered the down-sides of such fast switching.  Many vendors have reduced Cgd since.)

I see two key concerns.  First is just the magnitude of Vds spikes.  As Mads frequently points out, Vds spikes don't increase linearly with voltage.  Spikes at low voltage don't necessarily correlate to spikes at operating voltage.  However, at 30V your Vds spikes add another ~65V as shown on the first scope image, for peak Vds of ~95V.  This 95V/30V ratio will likely drop as voltage increases, but may not drop enough to keep Vds under 600V at 325V bus.

Second issue is the risk of high-frequency oscillations due to GDT winding capacitance.  Spike/ring reduction solutions will help here, but may not be sufficient.  For one of my projects with this issue, adding ferrite beads on the twisted pairs out of the GDT was sufficient (along with some ring-reduction efforts).  For the other, I changed to slower parts (fast IGBTs, but still much slower than FETs).  These projects were both switching close to zero-current points.  IGBTs are not likely appropriate here, as SSTC drive switches at high current.  Older slower FETs are an option.  I suspect that's how many older SSTC designs manage to work with wire interconnect.

For Vds spikes/ringing, my first suggestion is always to reduce stray inductance.  I recently posted an example of simple low-inductance half-bridge construction:
https://highvoltageforum.net/index.php?topic=1324.msg9795;topicseen#new
BTW, your GDT leads are nice and short, better than the above example I posted.

This can be improved further by using multiple parallel capacitors for C8 and C9.  Capacitor internal inductance is still a significant contributor to total parasitic inductance, so paralleling reduces inductance.  Adding film capacitors in parallel with C7 also helps, perhaps even more than multiple C8/C9 caps.  Even with this low-inductance layout, fast FETs can be problematic.  I use this general parallel-plane layout for all my H-Bridge designs.

Other techniques for reducing spikes/ringing:
Add TVS diodes across FET drain-source.
Add series R+C snubbers across FET drain-source.  (Resistor in series with a small capacitor, other end of resistor to source and other end of capacitor to drain, or visa-versa.)  This is common in many commercial circuits.
With either of the above, low inductance for the TVS or R+C connections is key to being useful.
It's not conventional, but I've also had good success recently with TVS + C snubbing.  This was a full-bridge, so I added bidirectional TVS diodes in series with capacitors from one output to the other.  Behaves much like an R + C snubber, but with less wasted power.

The differential probe will be quite useful.  It's long wire leads (long compared to a scope probe tip) can cause major errors in measuring high-frequency ringing (depending on how high the frequency is).  You can check by measuring ringing at low voltage with the differential and normal probes and comparing signals.

[Max Seiringer]

Thank you for answering, David!
I am using good old IRFP460 Mosfets for my bridge. I changed the 20 ohm resistors to 10 ohm and now the gate signal looks awesome again. Seems like the new 460's have a higher gate capacitance. Reverse transfer (miller) capacitance is noticable, but just a little bit.

I rebuilt the bridge according to your advice. Still sloppy wiring and pretty bad layout, but it now managed to get up to full mains (230VAC in my country) without blowing the FETs! I was really happy about the result until I saw some nasty racing arcs from the secondary over the primary carrying tube into the primary windings. Luckily the secondary is fine and the bridge survived. I guess this is because of the rather high permittivity of the drainpipe tubing (PP?), is it? Furthermore I will have to recoat my secondary with propper laquer.

Anyways, I am going to rebuild the bridge completely according to your (David's) advice and consturction layouts. In this sense I would call this discussion finished. Thank you all for your help (especially from you, David. Thank you for investing so much time into my build)! It has been a rousing success for me!

Kind reguards,
Max

[davekni]

Great to hear that your circuit survived 230V!  Congratulations!

Concerning arcs from mid-secondary, others likely have better suggestions that I do.  I had that issue on my DRTSSTC.  Fixed by more layers of coating on the secondary and dropping the primary 25mm to reduce coupling.  (I want more coupling, but needed to avoid arcs from the secondary.)

Polypropylene (PP) would be great for the coil, but pipes are more often PVC.  It could be polyethylene, which is also a good low-permittivity insulator.  I found some polyethylene drain pipe for my DRSSTC secondary form.