Author Topic: Ud2.7 how to stably track the upper / lower poles?  (Read 391 times)

Offline black.yang

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Ud2.7 how to stably track the upper / lower poles?
« on: June 08, 2022, 08:01:24 AM »
Hi Everyone, :)
  Since I manufactured my first QCW in 2017, a lot has happened in recent years.
But fortunately, I have been idle in my work recently, and I began to think about the "pole" operation of QCW
Generally speaking, ud2.7 will be locked at the upper pole of QCW to minimize the impact of arc parasitic capacitance.
 I refer to many posts here, and generally use two methods:
1:Adjust the primary coil detuning to a higher frequency to approach the upper frequency pole
2:Use "several startup pulses" to guide ud2.7 to work at the upper pole frequency
Based on the above two methods, I used LTSpice to do simulation content before actual production, and I will show it here.

Above, I simulated an ordinary QCW, and can see its primary coil current gain and phase Bode diagram. In the diagram, I marked the intersection of phase 1, 2 and 3 which are 0, of which the gain of intersection 1 and 3 is (lower&upper pole)the largest at the same time, and the intersection 2 will not be captured by ud2.7 due to its small gain.
So I began to wonder.
Because Bode diagram can describe the response of linear time invariant system, we can reasonably judge that ud2.7 will work at the upper and lower frequency poles indefinitely whenever there is disturbance
Next, I will perform time domain simulation on the same circuit (some parameters are adjusted to be closer to the reality) to verify this result.

I set the parameter scanning to give QCW 1-10 pulses of excitation signal (432khz) working at the upper frequency pole.
Normally, ud2.7 can be locked at the upper frequency point by doing this. However, in fact, by analyzing the FFT (I (L1)) channel current, it is still found that there is a peak at the lower frequency point, that is, the existence of the pilot pulse does not solve this problem


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Offline black.yang

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Re: Ud2.7 how to stably track the upper / lower poles?
« Reply #1 on: June 08, 2022, 08:28:32 AM »
Next, I designed a circuit diagram to guide the pulse. After running in LTSpice, I can see that it works well.

In the same QCW TC, through 5 pilot pulses, the coil can reach the perfect soft switching ZVZCS state at the upper and lower poles at the same time. It also verifies the frequency domain simulation Bode diagram (0 phase intersects 1 and 3 poles).

In the simulation system, the strategy of guiding pulses is undoubtedly feasible. (if you know the person who put forward this idea, please help me pay tribute.)
But my doubt is that if there is bistability in QCW TC, once there is some possible disturbance (arc shot on the ground, environmental change), there is the possibility of unstable tracking, and the arc capacitance of QCW TC will continue to increase, thus destroying the state of tracking at the upper pole. :(
Is there a design that allows the circuit to operate stably in a certain frequency range?
I consider implementing this function in CPLD. What I can think of at present is to generate a counter with fixed overflow time through Verilog, and the rising and falling edges of FB signal (TC driving square wave) will constantly reset this counter. Once it is lower than the upper pole frequency, the interrupt signal will be reset and TC will be closed.
However, this method is complex and may cause failure when the arc is long

I prefer to have a more stable method to track the upper pole, and specify the working state of ud2.7 through the unique characteristics of the upper pole, such as phase, gain, etc., so do you have any good ideas? Or have you ever done research in this field? I will implement these ideas in my CPLD driver circuit :P
« Last Edit: June 08, 2022, 08:33:29 AM by black.yang »
我的 Email:blackhv@foxmail.com

Offline davekni

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Re: Ud2.7 how to stably track the upper / lower poles?
« Reply #2 on: June 09, 2022, 06:30:59 AM »
Quote
I refer to many posts here, and generally use two methods:
Two other options to consider.  One is modifying UD2.7 to be self-oscillating at or above upper-pole frequency as in this thread:
https://highvoltageforum.net/index.php?topic=1914.msg14912#msg14912
Another option is to use a PLL design instead of UD2.7.

Quote
However, in fact, by analyzing the FFT (I (L1)) channel current, it is still found that there is a peak at the lower frequency point, that is, the existence of the pilot pulse does not solve this problem
Looks like your next post demonstrates (accurately) that this can work.  Energy at lower pole likely decays over the simulation time.  Perhaps a time-window on FFT would show this.  Also, if you want to reduce lower-pole energy, start with a half-width pulse (quarter-cycle) to avoid a net DC step at the start of operation.

Quote
I prefer to have a more stable method to track the upper pole, and specify the working state of ud2.7 through the unique characteristics of the upper pole, such as phase, gain, etc., so do you have any good ideas? Or have you ever done research in this field? I will implement these ideas in my CPLD driver circuit :P
PLL designs are probably the most common solution here, if you want to insure no pole hopping.  As USpring showed in some post, at heavy-enough arc loading it is possible for the upper pole to no longer be capable of ZCS operation.  In that case the only options are to permit non-ZCS or terminate the enable pulse.

Impressive use of LTSpice!  I learned a couple constructs from your posts.
David Knierim

Offline black.yang

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Re: Ud2.7 how to stably track the upper / lower poles?
« Reply #3 on: June 10, 2022, 08:20:37 AM »
Quote
I refer to many posts here, and generally use two methods:
Two other options to consider.  One is modifying UD2.7 to be self-oscillating at or above upper-pole frequency as in this thread:
https://highvoltageforum.net/index.php?topic=1914.msg14912#msg14912
Another option is to use a PLL design instead of UD2.7.

Quote
However, in fact, by analyzing the FFT (I (L1)) channel current, it is still found that there is a peak at the lower frequency point, that is, the existence of the pilot pulse does not solve this problem
Looks like your next post demonstrates (accurately) that this can work.  Energy at lower pole likely decays over the simulation time.  Perhaps a time-window on FFT would show this.  Also, if you want to reduce lower-pole energy, start with a half-width pulse (quarter-cycle) to avoid a net DC step at the start of operation.

Quote
I prefer to have a more stable method to track the upper pole, and specify the working state of ud2.7 through the unique characteristics of the upper pole, such as phase, gain, etc., so do you have any good ideas? Or have you ever done research in this field? I will implement these ideas in my CPLD driver circuit :P
PLL designs are probably the most common solution here, if you want to insure no pole hopping.  As USpring showed in some post, at heavy-enough arc loading it is possible for the upper pole to no longer be capable of ZCS operation.  In that case the only options are to permit non-ZCS or terminate the enable pulse.

Impressive use of LTSpice!  I learned a couple constructs from your posts.

Hi Dave,
Thank you for the link you sent me. I got inspiration from it.
By designing the positive feedback self oscillation of the comparator, the pulse guidance function can be well realized on ud2.7,
because the feedback strength will cover the start pulse :D

I reset my LTSpice simulation settings to avoid the step excitation to the system. When the system operates at the up / down frequency pole, the energy of the other pole is obviously weak, which makes me sure that the guidance pulse is working
As for PLL, I think it may be a available to working but not optimal solution.
Digital phase locked loop (DPLL) or analog phase locked loop need to lock the frequency / phase through k-mode counter or phase detector through LPF. This process takes a certain time.
The frequency of QCW TC will change with the influence of arc length, which may inevitably delay the loop, and hard switching will occur.
But in most cases, DPLL is a good choice. Maybe I am too cautious :-\

I think I will try to use simple combinatorial logic and use as few resources as possible to avoid FB working at the lower frequency pole.
I will show the results in this post.

« Last Edit: June 10, 2022, 08:23:49 AM by black.yang »
我的 Email:blackhv@foxmail.com

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Re: Ud2.7 how to stably track the upper / lower poles?
« Reply #3 on: June 10, 2022, 08:20:37 AM »

 


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