First SSTC build - some questions

[davekni]

That 20k will draw <1mA during normal operation, totally insignificant compared to 40A or whatever flowing through the 4.7uF cap.  Negligible effect on DC blocking.  (If the driver is accurately enough 50% duty cycle, it would run without a DC blocking capacitor.)

A differential probe measurement would work, but I was just thinking of a voltmeter.  Power up the bridge and not the driver and measure DC voltage.  Ideally it will be close to zero (low leakage current into 20k resistor).  That would be good, but leave me puzzled as to why so much 10kHz ring.

[zytra]

At full bus voltage (330VDC), with the driver off, I am measuring basically 0 across the resistor (see attachment).

I've then run the coil at roughly half that bus voltage (50VAC or so) and recorder a short video - the voltage seems to be under 1V, if you feel it's needed I can repeat that test at full bus voltage and with the scope attached in place of the voltmeter.

https://www.youtube.com/watch?v=_96_QEaFj88&feature=youtu.be


edit: is there a reason why that 10Hz seems to be less visible (perhaps even not present) toward the end of the pulse? It's very obvious at the very beginning of the pulse, and still very apparent through the higher current portion of the pulse but after that it's fairly dim if there at all.

[davekni]

I'd thought that the 10kHz ring was due to initial charge on the 4.7uF capacitor.  Clearly it is not due to that.  So anything I say about why it exists and why it decays away is only speculation.

Because the primary current always starts with a positive half-cycle (of the normal 170kHz frequency), there is a little bit of energy at 10kHz.  I don't think that is enough to explain what you are seeing.

The only other possibility that comes to mind is of primary current is coupling into the secondary current feedback CT.  Is that CT next to any primary wiring?

Or, possibly there's a resonance at the same ~10kHz of the secondary feedback CT and the 0.1uF DC-blocking capacitor between it and the diodes.  That seems unlikely, but you could try increasing the 0.1 uF to something larger and see if the ring frequency drops or amplitude reduces.

Anyone else with more SSTC experience know if this level of blocking-capacitor/primary coil resonance is typical?

[zytra]

The number of primary turns affects primary inductance, which affects the primary resonance. On some of my earlier tests with that 4.5" secondary, where it required super long pulse to get the coil going made those low frequency rings more difficult to see.



The secondary CT is a few inches away from the wires going to the primary.

[davekni]

A few inches should be plenty presuming the CT uses a ferrite core.

Yes, I remember that the slow-start plots had little ring.  That should perhaps be some clue to the puzzle, but I can't think what that implies at the moment.

[zytra]

Hopefully playing with the primary yields some more hints.


I am circling back to my full bridge layout questions, I continue reading and found cobaugh's thread which lead me to his website where all his specs were listed. Would I need a 4-diode bridge rectifier if the system was designed to be compatible with 240V split phase? Cobaugh is in the US as far as I know and since he mentioned 240V I suspect he is talking about split phase. However, he's using a 2-diode power rectifier. Unless he is using for something else? https://labs.cobaugh.io/hv/tesla/dr81/

[davekni]

The design you linked is voltage-doubling 240Vac to get 680Vdc.  It's exactly the same circuit as your doubler, just with parts rated for the higher voltage.

I'm also in US (Oregon).  My Marx generator and DRSSTC use 240Vac from a 40A cloths-dryer outlet (or 208Vac 30A three-phase when I'm at the local science museum).  Although the 240Vac is split-phase, neutral is not used.  (Unlike the above link, my system starts with a crude PFC stage.)

[zytra]

Thanks, I understand the doubler part of the circuit, I am just wondering about the rectification. A few days ago you mentioned that the schematics I had put together had 2 extra diodes. Your message suggested (I might have misinterpreted) that the 2 extra diodes could have been used in a circuit with split phase, which uses 2 hots that are 180-degree apart, no neutral. Like most heavy domestic appliances in the states, dryers, welder, ovens.

But looking at what cobaugh did, it looks like he may have only 2 diodes like my current circuit, which would means the extra 2 diodes in typical bridge rectifiers are not needed on split phase either.

These 4 diode rectifiers are used everywhere though which is why I was surprised by your comment. I knew it was possible to rectify with 2 diodes and thought the other 2 made the rectifier more efficient by not "wasting" anything. But considering these 4 diodes are this common I am just wondering why manufacturers aren't saving on 2 diodes if they can?

edit: here's what I am referring to: https://www.quora.com/There-are-two-different-methods-of-full-wave-rectification-One-has-two-diodes-and-other-has-4-diodes-Which-is-better-Give-reasons-why
I am not seeing the distinction between them mainly because both can be (are) used on the domestic 110VAC. The schematics with the center tap transformer shows 3 wires coming out of the transformer and diodes rectifying the 2 halves, but on most TC schematics using 2 diodes only show line and neutral.

edit2: I guess I should expand my thoughts a little bit more about the next project. One of things I am debating about is where or not I should (like this SSTC) have both the bridge and the rectification taking place in the same place (i.e. under the the coil); or if I should separate the power supply from the bridge. The latter was my plan as I was more or less planning to follow the quasar60 plans I had. But then doing that 2x2+1 layout for the SSTC showed me how compact it can be. I am still leaning toward the separate power supply which I can equip with ammeters and voltmeters to get readings without needing to be too close. If so the plan would be to design the full bridge for a maximum Vbus of 680 or so when ran on 240VAC, although it will run off 120VAC 95+% of the time.

[davekni]

Try simulating all the variations.  There are several free analog simulators, both on-line and downloadable.  My favorite is LTSpice - use it for home and work.

It all depends on what voltage you want.  If you are after 170V, then 4 diodes on 120V or 2 diodes on 240 split-phase.  If you want 340V, then two diodes on 120V (voltage doubler) or 4 diodes on 240V.  If you want 680V, then 2 diodes on 240V (voltage doubler again).  Of course, there's half-wave too.

The two-diode split-phase circuit is almost always with local transformers, not with split-phase line power.  With line power, split-phase makes even lower power factor on each phase.

Local or separate VBus DC supply is all your preference for packaging.  Personally I like separate for large projects.  I use the same 450Vdc 10kW PFC supply for two projects, and likely more in the future.

[zytra]

I need to try LTSpice, heard a lot of good things. I've used circuitlabs which has a GUI I like but I am not happy with the simulation tool.

I'll put together a full bridge of the same IGBT's for the SSTC. I am doing all this mostly to learn and experiment in I've always been drawn to, and I really like understanding how the various components and property work together. So testing the same coil with a full bridge is something I'd like to see before moving on to DR. I'll do a similar 3x2 layout as I did for the half bridge, and if I'm not mistaken with a full bridge the DC blocking capacitor is no longer needed. It'll be nice to see if there has been any change on the low frequency ring as well.

Edit: Actually I should be able to modify the one I build a few days ago. Just need to invert the N / L strips so that the other half bridge is on the edge rather than in the center, I'll do this in the morning
I forgot to post this: https://www.youtube.com/watch?v=JZnPGhCBrik&feature=youtu.be this is pretty much the best I could do so far, let's see if the full bridge improves this a little.

[davekni]

DC blocking is no more or less needed with a full bridge than with a voltage-doubled half bridge.  For half-bridge SSTC designs that don't have a center rail for VBus, a blocking capacitor is absolutely needed.  For a full bridge, and for your half-bridge with a center voltage rail, DC blocking is needed only to handle driver duty cycle variation away from 50%.  That variation is almost always enough to make DC blocking wise.

Have fun with LTSpice!  Learning is the point of experimenting for most of us.

[zytra]

I took the half bridge apart and started modifying into a full bridge (and keep the doubler) but then realized this is probably not going to work as I am short of a transversal trace on my 2x3 layout. So tomorrow I'll put together a new board, it's good practice anyway.

I've attached a quick draft of what I wanted to do, the red cross shows the trace that I can't keep moving to a full bridge, and why I need to redo my layout.

I've made an extra 2 small gate PCB's. Though I think I might reduce the resistor value from 6.8 ohm to perhaps half that considering the one GDT/driver is supplying 2 additional gates. I took a look at the gates with the scope and they looked a bit slower than with the half bridge.

[davekni]

Be careful about reducing gate resistance.  It provides dead-time during switching, not just edge slew rate control.  IGBTs generally turn on faster than turn off (due to stored minority carrier charge).  The diode keeps turn-off fast while the resistor slows turn-on.  If the full bridge is slowing gate waveforms, it is most likely slowing both, not increasing dead-time.  Rather than reducing gate resistance, I'd focus on reducing GDT and wiring leakage inductance.

[zytra]

That makes sense, I'll stick with those values then. I made a new GDT, and in retrospect I think I should have reduced the number of turns a little bit. I'll test it as is though, because the gates "looking" slow on the scope probably doesn't mean a lot, it will be better to evaluate this quantitatively when the coil is running.

[zytra]

So... I managed to mess up my layout and of course, I only realized that when checking everything after all components had been laid out on the freshly CNC'ed 5oz clad. haha. I need to find a good PCB software. Making those with Solidworks is far from ideal even though they're overall very simple.

Oh well there's always tomorrow.

[Mads Barnkob]

You have a very clean and low inductance layout. Regarding GDT construction I think you should take a look at the excellent practical guide from thedatastream (can only be found on archive.org now) https://web.archive.org/web/20200120153028/http://thedatastream.4hv.org/gdt_index.htm and if you want to change the gate resistor values, this is a super nice and simple guide to follow with a oscilloscope: http://www.richieburnett.co.uk/temp/gdt/gdt2.html

[zytra]

Thanks Mads, I'll study the GDT in more details tomorrow and compare today's screenshots to those with the half bridge to see if there is room for improvement.

Dave, do you have any thread or website that talks about your PFC power supply?


I kept the same primary, but I know I will to adjust it considering the higher voltage across it.
I removed the 4.7uF DC blocking capacitor. I still have the voltage doubler. And of course other than for the full bridge, everything else is the same. I kept the 6.8 ohm gate resistor like I had with the half bridge. In fact, I kept the schottky, zener and TVS exactly as it was, leaving only a different GDT (with twice as many secondaries).


My observations so far:
- Arcs seem better, I'll have to play with it more to be sure. No significant difference, though. At least not with the same primary.
- The high frequency stuff seems quite a bit more present
- The switching seems to be a little soft than before
- The low frequency ring is still there, weirdly. Although not as pronounced in the couple tests I had time to do. Not sure what to make of it since the 4.7uF cap is gone.

On the scope screenshots I have top/bottom left IGBT's on channels 1 and 2.
High side collector/emitter on channel 3.
Primary current on channel 4.

[zytra]

Regarding the low frequency ring, it's still there and depending on the bus voltage, it's more or less visible.

Here are 6 screenshots of the current waveform starting from 30VAC all the way to 105VAC (15VAC increments). And all of them have that same odd ~10KHz-ish in them.

[davekni]

First, it looks like the DC blocking capacitor is needed.  The gate-drive duty cycle is not close enough to 50% to get away without one.  Many of the scope captures show the current settling out to not centered around 0.  Depending on how low frequencies your CT passes, the real current may be much farther off.  The next-to-last capture shows Vge waveforms getting confused, likely by the current offset, which then resets the current DC component closer to zero.  One of the IGBTs may be coming out of Vce saturation due to the excess current, which generates huge power dissipation spikes in the IGBT.

The high-frequency noise through most of each half-cycle is likely coupling from the secondary arc into probe leads.  I wouldn't worry much about that.  The ring spike on Vge waveforms during switching is likely IGBT diode snap-off since switching is occurring after zero-current.  Not likely to be problematic given your nice low-inductance bridge layout now.

The low-voltage plots show Vge ringing after a burst ends at close to the same frequency as the initial current ring.  That suggests that the ring may be due to the 1uF DC blocking capacitor in series with the GDT primary.  Try adding damping parts across that capacitor as in the UD2.7 schematic, say a series 1uF + ~20 ohms in parallel with the existing 1uF.  That will likely fix the low-frequency ringing.  (Still a remote chance it is the feedback CT resonating with the 0.1uF capacitor, but GDT seems more likely now.)

Your GDT looks good from what I can see.  May not need as many turns for your operating frequency.  If reducing turns, the ~20 ohm damping resistor suggested above will be optimum at a lower value.  With fewer turns the GDT can handle more DC current, so damping may be possible with just a resistor alone across the 1uF DC blocking capacitor in series with GDT primary.  (I use 2 or 3-turn GDTs on large cores with no DC blocking capacitor.  I always have DC blocking on bridge output.)

[zytra]

Thank you, Dave.

Bridge DC blocking cap: I noticed the current waveform wasn't centered, and even double checked that the current probe had been zero'ed properly. I'll add it in the morning. DRSSTC always have the MMC in series with the primary anyway, I wanted to see if removing it took care of the low frequency ring.

Thanks for the advice on the GDT DC blocking cap. I didn't know it was possible to run without one with two drivers with opposing outputs through a GDT. I'll try adding a resistor/cap in parallel of the existing cap. I went a little hard on the number of turns exceeding what I had on the half bridge GDT. I'll prepare another one. I actually followed your suggestion of using cat 5 (1 wire of each pair in parallel as primary, and the other wire of each pair as secondaries) and that was pretty easy, compared to my first GDT where I used one twisted pair of cat5 that I ran through a 1/8" copper braid. It was nice and thin but a pain to run that twisted pair through the braid. One thing that's not great on that circuit is that it uses 12V input, so the GDT uses a ratio of 1:1.5 to raise the gate voltage to ~18V.