Mosfet Buffer Stage Questions

[Egg]

Hi, i was recently looking at the n/p channel mosfet buffer stage used in bridge drivers and honestly i got a little confused what exactly the capacitor/diode on the gate of the p channel mosfet does here. I tried simulating it and seems like the gate signal is shifted by (Vcc-Vpwm) volts to exactly suit the voltage needed to drive the p channel fet. But how does this happen?

My (possibly wrong) hypotesis is that r3 pulls the gate side of c1 to Vcc and when the pwm goes high there exists a ΔVcc-Vpwm on the cap and when the pwm goes low, the top side of the cap goes bellow Vcc to preserve the  ΔVcc-Vpwm potential across the cap thus turning the fet on. As an example if Vcc is 15v and the pwm signal alternating 6/0v, initially the voltage across the cap is 15v when the pwm goes high the extra charge flows to Vcc through D1 and the ΔV across the cap turns into 15-6=9v. Now when the pwm goes back low the voltage on the gate of the P fet goes 15-9v=6v thus turning the fet on, and so on..

Is this explanation correct?  If not can someone please explain it to me, i am thinking about this for a while now and i couldn't find much on the internet about it. Thanks.

[davekni]

Is this explanation correct?

Looks accurate to me.
Try simulating for a longer time period and/or reduce value of C1 to say 100nF.  Then you will see the need for D1.  D1 isn't needed for low duty cycles (short enable times), but is for longer times.