Feedback on new freewheeling driver schematic

[Mike]

Hi everyone,

In the quest for larger streamers I became interested in freewheeling controllers. Sitting on a pile of components to build a second UD2.7 I wondered what a minimal change would look like to convert it to freewheeling. I'm obviously aware of the pulse skipping work done by Dan in the UD2.9 and by Phil in the UD+ (amongst many others) but neither of these have much in common with UD2.7 component wise.

While thinking about the problem I came up with the attached schematic. I've deliberately tried to keep the schematic layout as similar as possible to the UD2.7 to make my intentions clearer. So far as I've seen my method of freewheeling is different from others out there (I doubt it's actually unique, I've just not come across it yet). The basic idea was that the over current event would invert the phase of one half of a full bridge. This has the advantage (?) of not relying on the flyback diodes as current continues to flow through the IGBTs. Because the IGBTs keep switching the current is shared between the top and bottom half of the bridge still.

At the moment I'm trying to maintain an option to select "normal" and freewheeling current protection modes (unfortunately this needed two jumpers), though I also want to maintain the same footprint as the UD2.7 so I might end up forgoing this, which brings me to my questions.

1) Has anyone with a flyback controller actually used the ability to revert to "normal" mode?
2) Can anyone see any flaws with my basic concept that I've clearly overlooked?
3) Does anyone see anything wrong with my implementation or have any other general feedback?

The schematic is still in a very early stage, so sorry if there are obvious errors (like the currently missing optical receivers) or blatantly wrong component values, I've not given it much  of a proof read yet and have deliberately not run the annotater over the schematic as I plan on matching the annotations of the UD2.7 where possible for simplicity sake.

Simulation is high on my todo list, but I'm a fan of collaborative development so was hoping to share early and get some feedback.

Thanks!

Mike

[davekni]

Simulation is high on my todo list, but I'm a fan of collaborative development so was hoping to share early and get some feedback.

Yes, simulation would be a great idea.  I think there are several issues.  Some are trivial, such as typo on UCC27243 which should be UCC27423.  Others affect operation.  LS86 will invert with one input high, making normal (not freewheeling) mode incorrect.  In freewheeling mode, I think the two HC74 halves will be timed to make only very brief pulses of freewheeling.  (Not certain - needs simulation or testing.)  Also, I see no way for interrupting to function in freewheeling mode.

This has the advantage (?) of not relying on the flyback diodes as current continues to flow through the IGBTs.

Current still flows through diodes.  IGBTs conduct current in only one direction.  Does not matter if IGBT is enabled or not when current is in reverse direction flowing through its internal anti-parallel diode.

With any such scheme using combinatorial logic feeding driver chip inputs, delay differences will make glitches on driver chip inputs.  If those glitches are wide enough to propagate through the driver, it will cause excess power dissipation and messy gate waveform edges.  Depends on logic speed relative to driver chip (UCC27423) speed.

Good luck with your freewheeling design.

[Mike]

First of all, thank you Dave for taking the time to look through the schematic and provide feedback, I really appreciate it.

Yes, simulation would be a great idea.  I think there are several issues.  Some are trivial, such as typo on UCC27243 which should be UCC27423.  Others affect operation.  LS86 will invert with one input high, making normal (not freewheeling) mode incorrect.  In freewheeling mode, I think the two HC74 halves will be timed to make only very brief pulses of freewheeling.  (Not certain - needs simulation or testing.)  Also, I see no way for interrupting to function in freewheeling mode.

UCC272423 - fixed, thanks.
LS86 inverting when high in normal mode - I could be missing something, but this was intentional and assumes that the two half bridges and GDTs are identical, including in phase so the inversion "corrects" the phase for GDT2. You make a good point though that this is different from current UD2.7 so it might be better to use the inverting output of the HC74 and a pull down resistor to allow a simpler retrofit, or allow it to be configured. I'll give it some though.
The other two issues need more investigation by myself. I think you're right about the interruption not working, but would also need to spend some time looking at the timing. Unfortunately I only get time to work on hobbies when the children are in bed, by which time I'm usually just about ready to go that way myself.

Current still flows through diodes.  IGBTs conduct current in only one direction.  Does not matter if IGBT is enabled or not when current is in reverse direction flowing through its internal anti-parallel diode.

Well, that just exposed an embarrassing oversight and is of course correct. It wasn't the main driver in any case, but I thought I'd "won something for free" in my rushed analysis.

With any such scheme using combinatorial logic feeding driver chip inputs, delay differences will make glitches on driver chip inputs.  If those glitches are wide enough to propagate through the driver, it will cause excess power dissipation and messy gate waveform edges.  Depends on logic speed relative to driver chip (UCC27423) speed

I assume you're talking about the addition of the XORs? This one is of interest because I naively assumed it would be OK considering I have the same number of gates between the flipflop and the UCC27423. There's the risk that the propagation delay being uneven between the two GDTs causes problems but that should only be a small error in zero crossing on one bridge. I've not looked into the differences in propagation delay between gates on the same chip, but will have a quick look into it. I was planning on using 74AHC logic everywhere and a quick search on TI's website shows a typical 5.5ns propagation delay and a maximum 6.5ns but no minimum. All gates are on the same chip though so we should (?) expect similar performance assuming the gates are loaded and routed similarly. Of course the same could be said for the two AND gates that are already present in the current UD2.7 though no doubt if it was marginal I could be exacerbating it.

Thanks again for the input, I enjoy working on designs with people, and the bouncing back and forth of ideas, hence my sharing so early in the process where many (most) would have waited till they had at least proofread the schematic and run a basic simulation 

[davekni]

LS86 inverting when high in normal mode - I could be missing something, but this was intentional and assumes that the two half bridges and GDTs are identical, including in phase so the inversion "corrects" the phase for GDT2.

When enabled it could work fine if GDTs wired to correspond.  When disabled, the lower two driver chip outputs will be low.  Upper two driver outputs will be high as in normal UD2.7.  Low disabled state is an issue for the AC-coupled connection from driver chips to FET gates.  That is why UD2.7 doesn't use the driver chip enable function.

I only get time to work on hobbies when the children are in bed, by which time I'm usually just about ready to go that way myself.

Yes, I remember those days   Now I live by myself and retirement is only a couple years out.  Of course, aging reduces my productivity to compensate for more available time.

I was planning on using 74AHC logic everywhere

Delays will likely be short enough then.  I'd thought about recommending 74AHC.  Just be careful to have a good ground plane (or approximation) and closely-placed and well-routed bypass capacitors.  74AHC tend to draw large current spikes during switching.

I was more concerned about transitions on one '86 input followed by a transition on the other input making a glitch on '86 output.  Without simulation, I'm not certain such cases exist, but I suspect so.  You are correct that delays generally match quite well within-chip for matched output loading.

Thanks again for the input, I enjoy working on designs with people, and the bouncing back and forth of ideas, hence my sharing so early in the process where many (most) would have waited till they had at least proofread the schematic and run a basic simulation 

You're certainly welcome.  It is nice to participate in designs without doing all the work myself.

[Mike]

When enabled it could work fine if GDTs wired to correspond.  When disabled, the lower two driver chip outputs will be low.  Upper two driver outputs will be high as in normal UD2.7.  Low disabled state is an issue for the AC-coupled connection from driver chips to FET gates. 

Of course, thanks for raising this. An annoyingly obvious thing to have overlooked. I inverted the logic to disable high.

I was more concerned about transitions on one '86 input followed by a transition on the other input making a glitch on '86 output.  Without simulation, I'm not certain such cases exist, but I suspect so.

A risk for sure, my simulation is a bit crude with the timings to rule this out so far (all logic devices running td=5n trise=5n tfall=5n). Both inputs are clocked from phase and pass through a single 74AHC device on their way so hopefully they should arrive at the "same time" minimising any glitches.

I've made a few other changes to address some of the bigger issues, thankfully I had the work of profdc9 to assist in this so basically ended up shifting from a UD2.7 as the base to a UD2.9 as Daniel had already figured out the logic required to enable the startup and retesting of the current limit on every cycle. I also used the previously spare XOR gates to keep the propagation delay consistent between the signals going to GDT1 and GDT2.

I also want to make a shout out to AeraCura_ who didn't want to clutter up the forum but noticed another basic mistake in the bridge rectifier.

Update schematics and simulation files (LTspice, zipped to keep the forum SW happy) are below. At some stage soon I'll take the time to clean the folder and upload these to github so other people can use them as a starting point for their own projects. I'm still keen on any additional feedback on any ideas that can improve or help avoid too many HW iterations. Otherwise I'm going to start assigning footprints and slowly making my way towards board layout!

[davekni]

Certainly progress!  I'd still suggest fixing a few things.

1) There is at least one mismatch between LTSpice schematic and ECB schematic.  IC6B-10 wiring differs, with associated IC4-2 to D3 cathode.

2) In freewheeling mode, H-bridge continues to toggle in-phase (almost zero net H-bridge output voltage) after interrupt goes away.  Even if you prefer this slow primary current decay, feedback gets weak and then stops.  GDT inputs never go to normal quiescent state of both low.

3) Q1 is serving no purpose I can dream up.  Isn't used in simulation case.  Might not be enough collector current to overcome IC5D-11 output given 74AHC logic.  Bad idea to short logic outputs anyway.  Recommend removing Q1.

4) Given 74AHC's high output current and fast switching, logic outputs charging capacitors through diodes will cause large current spikes.  I'd suggest adding a resistor (~470 ohms) between C29 and D16 anode, and another one in series with D3 (once D3 is wired per simulation).  Another option for edge-detect is to use a delay (low-pass filter) with AND gate between input and delayed+inverted input.

BTW, one inverter and one diode can be removed if IC4E-10 connects through a diode to IC4D-9.  Then IC4F, D12, D13, and R21 can all be removed.  This would be a change from UD2.7, but useful if you need another inverter.

Another BTW:  I think IC6A-4 could be connected to INTERRUPT instead of INTERRUPT_EDGE without changing functionality.  Works either way.  Just in case your other use of INTERRUPT_EDGE goes away and/or routing is easier.

That's all I see tonight.  Thank you for including LTSpice file.  That way I could probe other nodes to verify operation.

[Mike]

1) There is at least one mismatch between LTSpice schematic and ECB schematic.  IC6B-10 wiring differs, with associated IC4-2 to D3 cathode.

Thanks, corrected.

2) In freewheeling mode, H-bridge continues to toggle in-phase (almost zero net H-bridge output voltage) after interrupt goes away.  Even if you prefer this slow primary current decay, feedback gets weak and then stops.  GDT inputs never go to normal quiescent state of both low.

Hmm, this one is trickier to achieve while ensuring zero current switching. It's easy enough with another flipflop, but I'd like to avoid that if possible as I'm already worried about board space, so I'll see if I can find something neater.

3) Q1 is serving no purpose I can dream up.  Isn't used in simulation case.  Might not be enough collector current to overcome IC5D-11 output given 74AHC logic.  Bad idea to short logic outputs anyway.  Recommend removing Q1.

Agreed the use case is pretty unlikely. It was added to the UD2.9 to prevent another rising edge on the interrupt line from overriding the over current protection. I broke this slightly when adding IC5D to clean up the interrupt edge signal, I should have included a series resistor. It seems that if you had a normally operating interrupter this case should never happen. I'll probably end up removing it, but will at the very least add the series resistor!

4) Given 74AHC's high output current and fast switching, logic outputs charging capacitors through diodes will cause large current spikes.  I'd suggest adding a resistor (~470 ohms) between C29 and D16 anode, and another one in series with D3 (once D3 is wired per simulation).  Another option for edge-detect is to use a delay (low-pass filter) with AND gate between input and delayed+inverted input.

Good point, done. (I noticed I used a different RC combo for R13/C10 in the simulation from the schematic. It didn't matter much without the resistor in series with D3, but the time constant of the resistor in series with D3 and C10 becomes important to ensure proper startup I think I'll need a longer interrupt edge pulse to have sufficient timing margin).

BTW, one inverter and one diode can be removed if IC4E-10 connects through a diode to IC4D-9.  Then IC4F, D12, D13, and R21 can all be removed.  This would be a change from UD2.7, but useful if you need another inverter.

II like this and have implemented it. I had been thinking about doing away with the ability to populate both RX parts simultaneously and placing the two footprints on top of each other. Doing this saves space (and an additional diode, cap and resistor) but would potentially break mechanical compatibility which may or may not be important to some people. I'll see how I go for space when it comes to layout.

Thanks again,
Mike.

[davekni]

Hmm, this one is trickier to achieve while ensuring zero current switching. It's easy enough with another flipflop, but I'd like to avoid that if possible as I'm already worried about board space, so I'll see if I can find something neater.

Yes, I believe your goals require separate FFs, one for synchronizing OCD and another for synchronizing interrupt input.  The OCD input also needs something to hold the compare event from current peak until next rising current edge.  That could be handled with an R/C/D circuit or R/C/transistor, or with a set/reset FF made of two gates.  If this is smaller than a new FF package, might be useful.

BTW, I cannot think of any reason the two different UCC driver chips need to have matched input delays.  Thus the two extra AHC86 sections can be made available for other uses.

Edit:  I think logic size can be reduced by replacing both the AHC08 and AHC86 with an AHC157 chip.  Also allows using a single-output comparitor, since comparitor drives select line.  I'd recommend TLV3501 as a fast comparitor with rail-to-rail IO.  That is what I use.  Input circuitry can be simplified slightly given symmetric I/O ranges.

AHC157 outputs drive the four UCC inputs.  Interrupt after FF synchronization feeds AHC157 enable input.  Each of the AHC157 input pairs are one-high and one-low.  Lower set switch based on synchronized OCD (wire to Q and Qn of OCD FF, or perhaps one output and inverter to make phase-inversion easier).  Phase inversion could be done instead by inverting CT input wires or by adding a selectable inverter stage to comparitor output.

One more note:  In freewheeling mode, the half-bridge driven by lower UCC chip will be using its diodes and not IGBTs.  Upper half-bridge will continue using IGBTs as it does between freewheeling times.  If you want to spread out power dissipation to all four diodes and IGBTs evenly, then OCD inversion needs to alternate between driver chips.  Can't think of any way to do this without adding yet another FF package.  Perhaps not important enough to bother with making power even.

[Mike]

Yes, I believe your goals require separate FFs, one for synchronizing OCD and another for synchronizing interrupt input.  The OCD input also needs something to hold the compare event from current peak until next rising current edge.  That could be handled with an R/C/D circuit or R/C/transistor, or with a set/reset FF made of two gates.  If this is smaller than a new FF package, might be useful.

I had played with the idea of an RCD circuit for over current latching, but resetting it (via a bjt with a cap on the base) was getting complicated to the point where I think a FF would have taken less space. I also considered swapping the comparator for one with a latch, but that didn't save a whole lot.

The two input matching of the UCCs was mostly because the two AHC86 were sitting there unused and I supposed if the inputs were matched you wouldn't be splitting the error on the "perfect" zero current switching. I'm aware the other variables hugely swamp this effect, but as they weren't being used anyway...

Edit:  I think logic size can be reduced by replacing both the AHC08 and AHC86 with an AHC157 chip.  Also allows using a single-output comparitor, since comparitor drives select line.  I'd recommend TLV3501 as a fast comparitor with rail-to-rail IO.  That is what I use.  Input circuitry can be simplified slightly given symmetric I/O ranges.

On your suggestion I've had bit of a play here and I think it would save some space which is promising, but there is an issue with glitches on the output as the phase signals go straight though the AHC157 to the UCC, but are slower to propagate through the FFs to toggle the control line for the AHC157. With no mitigations this results in an ~20ns glitch when changing from freewheeling to normal modes and back again. I have attempted to mitigate this by implementing a small delay (inverters or RC time constants) on the phase inputs to the AHC157, though I don't really have the intuition to know how much of a problem the original wayward 20ns pulse is either... Overall I think this is my preferred path forward at the moment, it's definitely a neat solution so thank you for the suggestion.

P.S. on rereading your reply I realise I've built everything "backwards", compared to your actual suggestion.  I'll have another go and see if that can result in a solution without the glitching issues...

Edit:
A very simple change to implement the actual suggestion of davekni (rather than my half read imaginings) corrected the glitching issues I was seeing. Included in the "-2" files below.

[davekni]

Edit:
A very simple change to implement the actual suggestion of davekni (rather than my half read imaginings) corrected the glitching issues I was seeing. Included in the "-2" files below.

Yes, that is what I was attempting to describe.
I think it would behave the same if the interrupt edge detect circuit were removed and interrupt input wired directly to A3 preset input.  D input could remain connected to interrupt or wired low.

[Mike]

I think it would behave the same if the interrupt edge detect circuit were removed and interrupt input wired directly to A3 preset input.  D input could remain connected to interrupt or wired low.

I think you're right, I certainly can't see any reason that wouldn't work. I'll have a quick run through the auxillary circuitry looking at optimizations like the comparator, etc and then publish the updated kicad schematic.

[Mike]

Update time again.

Attached are the latest spice simulations including the phase adjustment, cleaned up resetting of the over current FF, presetting of the freewheeling FF state to ensure reliable starting, and me slightly improving the model for the gate drive and GDTs, mostly to prevent mistakes in logic going unnoticed while still trying not to let it get too complex.

I've also updated the Kicad schematic and had a first pass at layout. I'm not super impressed with the layout at this stage so might tinker around with it a bit more. The reason I say first pass as it was mostly an attempt to see how much space was available. There's a little bit of room left, but not a whole lot... There's also a little ongoing discussion around the feature set that can be had. I've removed the ability to use "non-freewheeling" mode. If you want to run with no phase lead you need to short out the inductor (no jumper). There's currently no startup oscillator.

I've included all the design files, but wouldn't recommend anyone actually builds this yet unless you really like debugging electronics. If you're bit of a layout wizz (I'm certainly not) and have any helpful observations they'd as always be welcome.

Cheers,
Mike.

[davekni]

Schematic is looking good.  A few small thoughts.

I'd use one more AHC14 stage to invert INTERRUPT to generate INTERRUPT-n.  As is, there are two different logic input threshold voltages monitoring the same HFBR output that may have somewhat slow rise and fall times.

I like your change to remove the phase-lead jumper.  Original UD2.7 is problematic if the jumper is missing or had a bad connection.  I'd suggest doing the same thing with the phase jumper J5.  It is easy enough to reverse feedback CT input wires instead.  Avoids one AHC14 inverter delay too - a very tiny improvement, but does make a tiny reduction in required phase lead.  Less delay needs less compensation.

TLV3501 is available in a 6-pin SOT23 package.  Lower supply lead inductances of that package are helpful for high-speed comparitor performance, and ECB space is reduced.  Lead pitch is a bit finer than SO-8, but not difficult to solder.  (Any accidental solder bridges are easy to remove with solder wick.)

I'll post alternate option for CT input stages (feedback and OCD) in a day or two.  Will include optional self-oscillation components around feedback comparitor.  I've discussed this in a couple other threads, but here's another attempt to explain the value of self-oscillation, and the one drawback I can think of:
With UD2.7, feedback comparitor inputs are biased around 0.2V apart when quiescent.  This voltage is determined by the 100k (R27) resistor current of ~14uA across clamp diode D1 (MBR0530, a schottky diode).  Some versions use normal silicon diodes (1N4148 or ...), which will have ~0.5V at 14uA.  When INTERRUPT starts, the H-bridge is enabled at one polarity.  The resulting half-cycle of primary oscillation must generate enough feedback current to generate more than 0.2V in order to cause the next half-cycle etc.  If feedback gain isn't quite enough (high CT ratio or high-impedance primary design or low-bus-voltage for bring-up testing), oscillation fails to start.  Failed oscillation will cause GDT core saturation and/or ringing with gate-drive output capacitors.  Since primary current is low, these "bad" IGBT gate waveforms generally don't fry anything.  Still, not great, and can interfere with low-voltage testing.
Also, in order to make startup likely, UD2.7 has a high 51-ohm feedback CT burden resistor.  This resistor dissipates significant power once primary current builds up, and requires a higher-current phase-lead inductor.
A self-oscillating feedback comparitor circuit reduces these issues.  It oscillates even with no feedback.  Allows testing with no H-bridge connected or with unpowered H-bridge or with 5V on H-bridge to verify GDT phasing.  If self-oscillation frequency is somewhat close to operating frequency, then primary current can build for several cycles before feedback must be strong enough to swamp internal self-oscillation.
AFAIK, the only down-side is the need to set self-oscillation frequency.  To be useful, it must be at least high enough to avoid GDT saturation.  It must be low enough to avoid gate driver overheating if feeding large IGBTs.  Those are the two requirements.  It is more useful the closer self-oscillation is to operating frequency.

[Mike]

Thanks again for all the input Dave.

I'd use one more AHC14 stage to invert INTERRUPT to generate INTERRUPT-n.  As is, there are two different logic input threshold voltages monitoring the same HFBR output that may have somewhat slow rise and fall times.

I'd actually considered this but figured the HFBR is plenty fast enough for it to make minimal difference. That said on further thought that clearly depends on the rising edge from the interrupter which is uncontrolled and there's no doubt that things are more consistent using one of the inverters, so I think it's the right thing to do.

I like your change to remove the phase-lead jumper.  Original UD2.7 is problematic if the jumper is missing or had a bad connection.  I'd suggest doing the same thing with the phase jumper J5.  It is easy enough to reverse feedback CT input wires instead.  Avoids one AHC14 inverter delay too - a very tiny improvement, but does make a tiny reduction in required phase lead.  Less delay needs less compensation.

Less delay is undoubtedly good. I have on more than one occasion needed to swap the direction of the phase on a CT, depending on the connector it can be between a few seconds and almost a minutes work. A jumper is much faster, but it's also optimizing an approximately one off task which is usually a waste of time so point taken.

TLV3501 is available in a 6-pin SOT23 package.  Lower supply lead inductances of that package are helpful for high-speed comparitor performance, and ECB space is reduced.  Lead pitch is a bit finer than SO-8, but not difficult to solder.  (Any accidental solder bridges are easy to remove with solder wick.)

This was actually my preference too. I have no trouble soldering SOT23s, my reason for choosing the SO-8 came down to availability today. I could find several thousand of the SO-8, but none of the SOT23 parts. I did consider doing a dual option footprint but the advantages mostly vanish (just as much PCB area and the extra trace length mitigates the internal inductance gains).

On the self oscillating circuitry the low voltage operation is enough to sell me by itself. I previously had a different CT for LV and HV, so that's a win straight away. I'll wait for your suggestions on the CT input stage. I have updated my simulation model with the AC-coupled negative feedback modifications you've posted elsewhere and it's a very neat solution.

If anyone else reading through all this has any opinions or suggestions I'd love to hear them.

Cheers,
Mike.

[davekni]

This was actually my preference too. I have no trouble soldering SOT23s, my reason for choosing the SO-8 came down to availability today. I could find several thousand of the SO-8, but none of the SOT23 parts. I did consider doing a dual option footprint but the advantages mostly vanish (just as much PCB area and the extra trace length mitigates the internal inductance gains).

Yes, I now see the availability issue.  I sometimes order parts directly from TI.  Usually a bit cheaper than through distributors if buying enough to amortize shipping cost.  More available too.  However, TI has only 4 of the SOT23 parts in stock.  Another option is to use TLV3502 (dual comparitor) in SO8 package, with other half used for OCD.  Not sure about layout considerations, however.  TLV3502 doesn't appear to be widely available either, but TI has 162992 in stock.

Here's the alternative input schematic I'd promised, first in image format to include inline:

There are two mostly-separate ideas in the above schematic.  One is for feedback input including self-oscillating version (top half of schematic).  Other is for OCD.

Values are shows for self-oscillating version.  R3 and R4 are do-not-stuff (10E9 for simulation).  Simulation is set up for ~160kHz.  Self-oscillation range is about 100kHz to 300kHz as shown (50k POT for R12).  Change C5 value for lower or higher frequency ranges.  Phase lead is adjusted by POT R8/R9.  About 450ns phase lead as shown.  Maximum range is as high as makes sense even for very-slow IGBTs, over 1.5us at low frequency.  If minimum phase lead isn't low enough, L1 value can be decreased and/or a resistor added in parallel with L1.

Scope monitoring of primary current is possible with the test points shown across R10.  Net resistance for scoping is 5.07 ohms (6.8 ohms paralleled with 20ohms from below OCD circuit).

For operating without self-oscillation:  Change R3 and R4 to 10k, change C5 to 10nF, and remove R11 (and R12 if desired).

Lower portion of schematic is an OCD option.  It senses only the positive half-cycle.  Since OCD is sampled on rising edges of "Phase" signal (falling slope of current), OCD is sensed just before being sampled.  There is little value in sensing negative half-cycle.  A positive half-cycle always follows a negative half-cycle before OCD is sampled.

I've dreamed up several variations of this OCD including ones that use dual comparitors to sense both half-cycles.  This is the one that seems best to me.  Threshold voltage is fixed at 2.5V.  OCD is adjusted by attenuating the current sense signal with a POT.  As shown, adjustment range is about 0.52A to 1.03A (~500-1000A for a 31*31:1 ratio CT).  R10 value can be changed to alter this range (or CT ratio changed).  R10 could be left open initially for low-current testing, for ~0.14 to 0.28A range.  Removing or increasing R10 does reduce phase-lead (more resistance for given inductance).

D3 and D4 forward voltage drops roughly cancel.  Matching is never perfect.  That is one reason for 2.5V threshold rather than adjustable threshold.  A threshold adjusted close to 0 would make diode matching error more significant.  I can avoid the diode matching requirement with other designs, but with more complexity and/or other possible concerns.

LTSpice source added in ZIP format:
udx3.zip

Please feel free to make suggestions or ask questions.  Use whatever portion you want.  Other designs may decide to try other portions in the future.  I'm personally fond of avoiding extra CTs.

[Mike]

Wow, thanks.

I'm a huge fan of the phase adjust method. I'd been playing with adding too much phase, then compensating with a variable delay, but this so elegantly sets the correct phase right at the point of measurement which is a nice improvement.

I agree a single CT is much nicer, and sampling on only the positive phase makes perfect sense. I do have two questions about the proposal there though.
1) how do you set the over current limit, it looks as though you'd have to have a current flowing through the circuit and adjust the potentiometer semi live (you could use a DC voltage at the CT input I suppose). 
2) Is there an particular reason you use a low impedance at the input to the OCD section of circuitry? Couldn't this equally be a 10k potentiometer for example?

Cheers,

Mike.

[davekni]

1) how do you set the over current limit, it looks as though you'd have to have a current flowing through the circuit and adjust the potentiometer semi live (you could use a DC voltage at the CT input I suppose).

Yes, I was thinking DC voltage, such as connecting CT input to +5V (presuming an extra 200mA is available), then measuring 10ohm POT wiper potential.  Thank you for the reminder.  I'd intended to add a test point on pot wiper node (perhaps paired with a ground point).  Forgot about that by the time I got to drawing the schematic.  A test point on +5V would be handy for this too (which could be paired with a CT input test point for easy jumper connection).

2) Is there an particular reason you use a low impedance at the input to the OCD section of circuitry? Couldn't this equally be a 10k potentiometer for example?

Pot needs a reasonably-low resistance so that load of R20 (331 ohm) doesn't affect trip point much.  As is, R20 load increases OCD trip current by 1-2%.  Of course, R20 and R19 could be increased too.  That would probably be fine to a point.  10x higher impedance through that circuit would probably be fine presuming a clean ECB layout.  Low impedance makes coupling from adjacent traces insignificant.

Faster feedback comparitor is obviously more critical for layout.  I tried to keep impedances there as low as practical too.

[Mike]

I've incorporated the phase feedback and some of the concepts from your OCD circuitry, though the OC circuitry is currently quite different from your proposal.
I reused the diode drop cancellation trick (though implementation differs slightly) but kept the variable reference. This is mostly due to me being quite fond of the simplicity of just setting a voltage, and it's done, no jumpers required. I'll concede there's more likely than not something I've missed but the diode matching error seems a small issue since they should be <100mV apart which is only 2% full scale error assuming we keep the parts at similar temperatures.



As always I really appreciate the feedback and assistance, I've found this whole development a really enjoyable and enlightening experience so far.
Mike.

[davekni]

This is mostly due to me being quite fond of the simplicity of just setting a voltage, and it's done, no jumpers required.

Yes, excellent point.  Simplicity of use and understanding is a key criteria that I tend to overlook.

I'll concede there's more likely than not something I've missed but the diode matching error seems a small issue since they should be <100mV apart which is only 2% full scale error assuming we keep the parts at similar temperatures.

If you want to improve matching, make the 5V divider (R10, R17, and R21) stiffer (lower values).  Part of D8's forward voltage drop shows up as changes in the divider voltage, rather than all on comparitor input as desired.  If the divider is much stiffer than R20 (10k), then most of D8's drop shows up at the comparitor to accurately compensate for D1's drop.

Even though it is copied from UD2.7, I'd remove C8.  It makes a momentary short circuit on comparitor output during transitions, causing ground-bounce inside the comparitor.  If glitch filtering is necessary, it should be on the input side of comparitor, or isolated by a resistor to limit current.

Finally, one theoretical concern that may be a non-issue in practice:  If CT current ever exceeds ~1.2A, comparitor input is pulled above 5V supply.  In normal operation this shouldn't occur unless primary current rises very rapidly from one cycle to the next.  OCD would shut down at 1A for max setting.  If this is of any concern, adding a small resistor (100 to 1k) in series with comparitor "-" input would limit current.  For even more protection, add a BAT54 (schottky signal diode) to 5V supply after resistor.

[davekni]

In case it is of interest, here's another OCD option with direct OCD setting by voltage and no diode voltage canceling:

BAT54S (very common schottky signal diode series pair in SOT23 package) forward voltage is generally less than what would forward-bias substrate diodes within the comparitor.  If you want to be even more certain, another BAT54S could be added on the right side of R4 (directly on comparitor "-" input).