Upper audio frequency interruption of HFSSTC

[uzzors2k]

Hi all, I was working on a new class E HFSSTC PCB with an interrupter input some months back, but was stumped by a problem. Perhaps some of the clever minds here have an idea!
The fundamental issue is that when I interrupt my class E Tesla coil at a high frequency (1-2kHz or so), the main MOSFET explodes. I encountered this while running through all the notes on my keyboard with a MIDI interrupter. Schematic: HfsstcDriver_rev3_uzzors2k.pdf

Now I ~think~ it occurs because of ringing in the GDT. From oscilloscope tracing, and verified through simulation, I see that the leakage inductance and
DC blocking capacitance resonate when the drive is interrupted. This resonance is a few volts, and maybe enough to turn the MOSFET partially on, causing heavy losses.
I have a solution for this which is to short the GDT during off time in order to quench the circulating energy. But there are two issues here.

1) Is the GDT ringing a likely culprit for the MOSFET deaths, or could it be something else? I've tried modelling more of the system, but without great success.
2) Is there any practical way to avoid the large circulating resonant current in the GDT? Some leakage inductance will always be present with a GDT.

I had previously attempted using a gate driver chip directly, but this failed catastrophically when the drain voltage was increased.
I have a suspicion this might be related to the problem with the MOSFET dying at higher interrupter frequencies.

Comparison of the observed waveform and the simulated waveform. plot_gate_ringing.pdf

[davekni]

There appear to be several issues.  First, the scope capture doesn't appear to match your schematic.  Either that or the GDT leakage inductance is really high and making a series resonance with gate capacitance at your SSTC operating frequency.  Did you change to a 1:2 GDT ratio?  How is it wound?  0.94 coupling factor is extremely low for a GDT.

For interrupting, you need to drive both sides of the GDT with separate driver chips.  The disabled state needs to drive to the center voltage, not to one rail or the other.  With two drivers, both low (or both high) produces that center-voltage output between enable pulses.

The low-frequency parasitic resonance you see is not leakage inductance, but rather GDT parallel inductance resonating with the DC blocking capacitor.  Adding an R + C network across the existing C as in UD2.7 will damp that resonance.

One final possibility, though unlikely if schematic values are accurate.  At turn-off, the FET drain inductor L1 combined with output capacitor C12 will form a resonant circuit.  If average FET current is high enough, that resonant circuit could ring high enough at the end of enable pulses to hit 600V.  That would take ~20A average current with your values, so seems unlikely.

[uzzors2k]

The GDT is bifilar wound on a Toroid, eight turns. I guess the simulated coupling factor is unrealistically poor, I looked up a reference just now to see what normal ranges were again. Practical GDT designs the site seems to be down, but I found it on the WaybackMachine. I simply tuned the coupling factor to get the simulation to roughly match the scope shots. Thanks for the R + C damping network tip, that will certainly help.

[davekni]

With your bifilar 1:1 GDT, there must be a large overshoot on the gate waveform to get from 15Vpp input to ~30Vpp output per your scope trace.  It would be worth zooming in to the gate waveform.  You will likely need a small series resistor between gate and GDT to damp that overshoot.

Once overshoot is removed, the gate waveform will be +-7.5V, a bit marginal for turning on the output FET (Q1) completely.  Most power FETs are specified for 10Vgs, and 12Vgs is often used to get maximum performance.  That's another reason for using two driver chips with GDT primary between two complimentary outputs.  With two driver chips running on 12V, Vgs becomes +-12V.  Even +-15V is fine for FETs as long as overshoot is minimized.  The two driver chips also allows for proper disable for interrupting.

[uzzors2k]

I thought it would be good for posterity to update this thread with what I ended up doing to solve the problem. Through my tests with different gate driver topologies I eventually tried a DC restoration circuit on the secondary side, to boost the voltage at the gate well past the threshold voltage. This is essentially just a series capacitor and reverse biased diode across the mosfet gate. Using this one can tune the DC level, and to my pleasure it also seems to dampen the gate ringing I was experiencing. Two birds in one stone!

http://uzzors2k.com/index.php?page=4MHzclassE1

[davekni]

Since your gate drive circuit appears to be fine with the 18R load, looks like a good solution.  It forms a low-pass filter with GDT leakage inductance, so will reduce any overshoot or undershoot on gate waveform.  (Not sure if you were having any of that issue, or just the low-frequency ring caused by GDT parallel inductance.)  The low-frequency ring (80kHz) was around 30 ohms coupling-capacitor impedance, so swamped by 18R load.

You could probably reduce the 100nF coupling capacitor value some to reduce Vgs decay time at turn-off, given your 4MHz operating frequency.

Your diode clamp is similar to my HFSSTC designs.  I add a zener diode (paralleled with capacitor) in series with the clamp diode to get some negative Vgs swing for the SiC FET.