ZVS driver won't oscillate

[AstRii]

Hello,
I had two spare STE40NK90ZD MOSFETs (https://www.st.com/resource/en/datasheet/cd00003691.pdf), three very nice snubber capacitors 1uF 1200V rated for 30Arms and some 10mm copper tubing.
Exactly the components needed for a powerful ZVS driver.
So this is what I ended up building:




Some differences from basic ZVS circuit:
- I had to drastically lower the Gate resistors, as my Gates have well over 25nF of capacitance.
- Added a linear regulator to lower the voltage for Gate resistors. It still dissipates heat but LM317 can be at least mounted on a heatsink.
- Unfortunately one of my ferrite cores has a slight crack in it. I glued it together but its inductance is slightly lower than the second (otherwise identical) inductor.
- I wanted the ZVS driver to start after the bus capacitors get charged for more reliable oscillation start, that's the circuit on the bottom. It pulls the Gates down and waits for roughly 0.5s before turning Q2 and Q3 off.

Unfortunately the ZVS driver doesn't want to start oscillating and only latches and shorts my lab bench power supply.

My thoughts:
- Is it a problem that L1 and L2 are different inductances? It shouldn't matter, right? After all this circuit can only start up thanks to asymmetries.
- Maybe 25nF of Gate capacitance is too much?
- Maybe only 50uH and 38uH is too small inductance? Does it matter? How would we even decide on optimal inductance anyway?
- I know ZVS drivers won't oscillate if the coupling is above 0.86. Here I start the ZVS without any load on the work coil, so the coupling is 0 or rather undefined.
- I tried disconnecting the LM317 from the common heatsink. Maybe the "TAB" pin which is connected to "OUTPUT" shorts something on the heatsink? (Nope, didn't help).

NOW THE WEIRD PART
If I remove the "soft-start" circuit, remove the C1 bus capacitor, remove the linear Gate supply, connect the resistors straight to Vcc and I suddenly connect lab bench power supply voltage to the circuit, it starts
Here it is on the video:

https://youtube.com/shorts/5Ox6IoyH1MY?feature=share

It even starts on low voltage (all the way down to around 6V).
And it oscillates quite nicely:

Tank current ~50A/div


Gate waveforms


Gate and Drain of one of the MOSFETs

It only starts if I suddenly connect power from a lab bench power supply. If I wire it up beforehand and then I press "output" button on my PSU it does not work.
I tried to research the topic a bit and I haven't found anyone having the same issue. Most common ZVS driver issue people have is one of the FETs connected backwards

I would be very glad for any help on how to make the circuit start reliably. Do you think of capturing any waveform which could help debugging this issue? I will gladly scope it.

[davekni]

- Unfortunately one of my ferrite cores has a slight crack in it. I glued it together but its inductance is slightly lower than the second (otherwise identical) inductor.

If a crack is making that difference, do you have an intentional gap in ferrite core?  An ungapped ferrite core will saturate at low current.

- I wanted the ZVS driver to start after the bus capacitors get charged for more reliable oscillation start, that's the circuit on the bottom. It pulls the Gates down and waits for roughly 0.5s before turning Q2 and Q3 off.

This exactly opposite to what is needed.  Gate supply needs to be on first, then main supply.  As you've found, a sudden start of both simultaneously can work too.

- I know ZVS drivers won't oscillate if the coupling is above 0.86. Here I start the ZVS without any load on the work coil, so the coupling is 0 or rather undefined.

The 0.86 limit is for transformer-coupled ZVS output coil.  The real requirement is a minimum resonant Q.  0.86 or lower coupling in a transformer ensures Q remains high enough over any output (transformer secondary) load impedance.

A couple threads that may be useful:
https://highvoltageforum.net/index.php?topic=831.msg5491#msg5491
https://highvoltageforum.net/index.php?topic=1227.msg8993#msg8993
There's also a very long thread on the common 48V induction heater boards or kits.  I'm guessing you've already looked at some of these.

[AstRii]

If a crack is making that difference, do you have an intentional gap in ferrite core?  An ungapped ferrite core will saturate at low current.

The inductors I'm using do not have an air gap, not sure if I understand here how gap helps with saturation.

This exactly opposite to what is needed.  Gate supply needs to be on first, then main supply.

This is exactly what I wanted to hear! I thought it's the opposite case... I have updated the circuit the following way and it works!


This way it always starts up after some delay, exactly the behavior I wanted.
Thanks Dave!

[davekni]

The inductors I'm using do not have an air gap, not sure if I understand here how gap helps with saturation.

Links to a couple web pages that explain the need for gaps better than I would manage:
https://www.mag-inc.com/Design/Design-Guides/Inductor-Cores-Material-and-Shape-Choices
https://electronics.stackexchange.com/questions/350711/why-do-we-want-gap-in-the-core-material-while-designing-inductor
You can likely find others with an internet search.  As is, will work fine at low power.  At high power (load inside work coil), cores will likely saturate and inductance drop dramatically.  Can't say for sure if inductance will drop enough to cause serious issues or not, but I'd guess yes.

This is exactly what I wanted to hear! I thought it's the opposite case... I have updated the circuit the following way and it works!

Glad to hear that its working!  Two recommendations for your start-up circuit:
1) At higher VCC, I expect either Q2 or D5 will burn out.  Needs some current limiting.
2) Hysteresis in the start-up circuit would help.  If you start at higher VCC and with load inside coil, Q1 may dissipate too much power for too long as it ramps from off to on state.

This way it always starts up after some delay, exactly the behavior I wanted.
Thanks Dave!

You are certainly welcome!

[AstRii]

Those are some very nice explanations, definitely worth reading through all of it.

Glad to hear that its working!  Two recommendations for your start-up circuit:
1) At higher VCC, I expect either Q2 or D5 will burn out.  Needs some current limiting.
2) Hysteresis in the start-up circuit would help.  If you start at higher VCC and with load inside coil, Q1 may dissipate too much power for too long as it ramps from off to on state.

Actually I made a mistake in my schematics, I missed a 1k resistor in between Q2 and D5. Sorry, it should have been this way:


As for the Q1, I actually used 4x IRFP9110 in parallel and placed them on a heatsink, so I'm not much worried about them failing.

[davekni]

Looks good.  Have fun heating things!  Would be interesting to see scope captures as load increases to see what effects show up with inductor saturation.

For testing and experimenting with inductors at higher currents, my favorite technique is ring-down of an L//C circuit.  Connect scope across inductor, charge a capacitor, then connect capacitor across inductor.  Motor-run capacitors are good for larger coils, available up to 70uF or more.  Newer ones are usually polypropylene.  Look at the waveform shape and frequency as the voltage and current decrease during ring-down.  At high currents when core saturates, waveform will be flat-topped (closer to square rather than sine) and higher frequency.  As current decays, frequency drops (inductance increases) and waveform becomes more sine shaped.  For some core materials such as silicon-iron, frequency may increase again at very low currents.  This technique sometimes requires a few repeats to get a clean ring-down waveform (to get clean contact without bounce back to open during waveform duration).  I've built a couple electronic switches for this purpose, TRIAC for higher voltages and FET for lower voltages, with gate supplied by a switch and battery through schmitt-trigger circuit.

[AstRii]

So I have another problem with the driver. It works well until the input current is too high. At over 20A input current, the drivers just shorts the power supply. Thankfully FETs survived every time.
This problem is only caused by input current, it is not dependent on input voltage, as soon as current reaches around 20A and more, the problem occurs.

My theory is that this happens because the Uds of one of the transistors becomes too high, combined with forward voltage of the gate-drain diodes the voltage is too high and the Gate of opposing transistor won't get pulled down.
I saw this schematics on https://www.vn-experimenty.eu/vn-zdroje/zvs-driver-modified.html

It says on the website that C2/C3 together with D2/D4 pulls down the voltage on the Gates to negative voltages. But I don't understand how that works and my simulation in LTspice doesn't work if I add these components.
Can anybody explain to me the working principle behind this?

[davekni]

My theory is that this happens because the Uds of one of the transistors becomes too high, combined with forward voltage of the gate-drain diodes the voltage is too high and the Gate of opposing transistor won't get pulled down.

That is the most likely explanation.  It's what limits power in the cheap Chinese induction units.  They add cooling fans to squeeze slightly more power out of a circuit.  Cool FETs have lower Rds-on and higher Vgs threshold.
Other possibility:  Drawing more current inherently means Q of resonant circuit is dropping.  If Q gets too low, voltage will not ring down low enough to switch FETs.

It says on the website that C2/C3 together with D2/D4 pulls down the voltage on the Gates to negative voltages. But I don't understand how that works and my simulation in LTspice doesn't work if I add these components.

Try adding some initial conditions to your simulation.  Since most device models do not include any noise, it is possible for a simulator to stay at an initial perfectly-balanced condition even though unstable in reality.  For example, start with a voltage across C1 and zero current through the two 3-turn inductors.  If it still doesn't function, at least you will see the ringdown waveform of the primary resonant circuit.  With that waveform you can explore why it doesn't produce proper feedback.  Will be easier to understand in simulation than for me to explain in words.
Also may help to start with the main 100V supply at 0V and ramp it up during simulation.  Best to have gate supply (30V) on before main supply in real use too.

I tried a similar gate voltage shift idea in simulation (but not built).  Starts with my ZVS circuit that uses small FETs for gate drive instead of diodes.

[AstRii]

I have measured G-S voltage reaching over 4.5V when drawing over ~23A on the input side, this likely confirms that the issue here is the high Uds. I'm quite confident about Q factor of my circuit, I have very low ESR MMC and liquid cooled work-coil. I've seen people with much higher resistive circuits with much higher loads than what I'm trying and oscillations didn't stop for them.

I would very much like to implement such "voltage shift" idea to my circuit as well, to secure Gates with lower voltage during off state, but I do not understand how adding capacitor and zener diode ensures negative voltage off-state Ugs, therefore I'm not able to choose correct values of C and Uzener. I would very much appreciate an explanation of how this works.

[davekni]

Simulation would still be the best way to understand, but I'll try explaining in words.  This will be somewhat a tutorial in zener diode use.
First, an aside:  Most "zener" diodes are actually avalanche-breakdown diodes.  Only the low voltage ones are true zener diodes.  Zener diodes have a softer voltage knee (higher resistance).  Voltage across a zener varies more with current than for most avalanche-breakdown diodes.  For that reason, I try to avoid "zener" diodes under 6V.  I'll use the phrase "zener diode" to refer to avalanche-breakdown diodes too, since that is common usage.

Zener diode use usually falls into two categories.  One is for transient clamping, as in TVS diodes used to protect IGBT and FET gates.  (TVS diodes are avalanche-breakdown diodes specifically designed for high transient current.)  The other category is as a fixed voltage.  Usually zener diodes for fixed-voltage use are paralleled by a capacitor as in this circuit.  As long as two conditions are met, the zener can be viewed as a DC voltage source.  Condition 1 is that average current is flowing into the zener.  (Zener can't actually generate power.)  Condition 2 is that the parallel capacitor is large enough to minimize voltage drop when current is flowing out.  Those conditions should be met here for D2 and D4 (3.9V zener diodes).  That is the expected reduction (negative offset) in gate voltage.  As above, I'd suggest increasing that to 6.2V for better regulation.
D1 and D3 are used in the first category, as transient clamps.  Though here the "transient" is half-cycles.  Diodes D11 and D12 isolate FET gates from the capacitance of D1 and D3.  Large zener diodes and especially TVS diodes tend to have high capacitance.  Fast signal diodes D11 and D12 allow larger D1 and D3 to remain charged to 15V.  (So in that sense perhaps D1 and D3 are closer to the second category of zener use per my above definitions.  My claim of two categories is somewhat arbitrary.  However, I'd still put D1 and D3 in my first category.  They are used to clamp voltage.  There is no requirement for them to remain charged between half-cycles.  They just happen to due to their capacitance.)

BTW, I agree that low Q is an unlikely reason.  Even a bad work coil and bad capacitors will have plenty-high Q.  It would require the work piece to lower Q enough.  The flat pancake coil of an induction stove element with an iron pan directly on top can get to quite low Q.  Waveforms become quite distorted (not that sine shaped any more).  Drive circuits are usually class-E.