Author Topic: HFSSTC design help and questions  (Read 183 times)

Offline Power-Max

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HFSSTC design help and questions
« on: June 27, 2021, 08:47:55 AM »
I got a whole bunch of FCA35N60 MOSFETs, rated 600Vds and 90mOhms. Although the capacitance are a bit high on it.

I was thinking about making one of those fancy HFSSTCs with it. I wound a secondary and it clocks in at around 7-8 MHz when energized from a function generator.

The circuit I'm using is the very simple one with the DC bias voltage applied to the gate, a small capacitor on the gate connected to ground, with a series LC primary connected drain to gate.

The big problem with this type of circuit seems to be the the unregulated feedback. MOSFET gates are notoriously picky about voltages, and I have to tread carefully so as not to overdrive the gate or exceed 24Vpeak-peak or thereabouts. I thought about redesigning the circuit to operate as common gate, so that the input impedance is very low and the energy gets recycled into the oscillator, but the problem is it's stable (I think common base amplifier is not inverting and hence stable) I need to find a way to invert the phase.

But anyways, regarding the normal circuit, should the ratio of the additional gate-source capacitance and the series LC capacitance be conserved? I most versions of the schematic I came across appear to use 100pF for the tank capacitor and ~4nF for the gate-source shunt. Can these values be scaled proportionally to increase or decrease the operation frequency? I already killed a few of my FETs messing about lol
« Last Edit: June 27, 2021, 08:27:56 PM by Power-Max »

Offline davekni

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Re: HFSSTC design help and questions
« Reply #1 on: June 27, 2021, 06:48:17 PM »
FCA34N60 looks like a fine part for HFSSTC use.  100pF to 4nF is 40:1 ratio.  Adding in ~1.3nF of gate capacitance gives 100pF to 5.3nF or 53:1.  20Vpp on the gate allows only 20 * 53 = 1060Vpp on primary coil.  That seems a bit low, but I don't know your specific design.

To avoid frying parts, start with simulation, LTSpice or other such program.  Much easier to iterate designs in simulation than with physical parts.

TVS diodes gate-to-source can help.  They will quickly overheat if driven too hard, but will protect FETs from transient gate over-voltage.

Make sure the 4nF (or whatever you end up with) capacitor has low inductance and is connected directly to the FET source.

Are the FETs frying with just gate-source fried, or drain-source or all three?  If the issue is excess gate voltage, usually only gate-source shorts.  The FETs are specified at +-30Vgs maximum, higher than many FETs.  Your issue may be excess drain voltage or excess power, which are more likely to result in drain-source shorts (and often gate too, so all three pins shorted).
« Last Edit: June 27, 2021, 09:52:44 PM by davekni »
David Knierim

Offline eli

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Re: HFSSTC design help and questions
« Reply #2 on: July 18, 2021, 09:33:40 PM »
just add a zener, it hasn't too many capacitance to mess something up. my design uses two 12v zeners back-to-back. not a supressor, it has a big capacity. also, with 600v d-s you will be able to supply it 70v max, my irfp260 drain sees 350v on it at just 35v, i still don't know why it doesn't burn. anyway, it should be good enough. zeners must be as close to gate and source as possible. also, about design improvements, make the gate voltage divider work from separate 12v source, that way you can interrupt it, ramp it and make a lot of nice stuff. the tuning will be much easier with some scope. good luck:D

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Re: HFSSTC design help and questions
« Reply #2 on: July 18, 2021, 09:33:40 PM »

 


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