Author Topic: HFSSTC with fixed crystal-controlled frequency  (Read 586 times)

Offline davekni

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HFSSTC with fixed crystal-controlled frequency
« on: May 22, 2021, 05:13:08 AM »
Finally having some success with a fixed-frequency HFSSTC.  Unlike most coils, gate drive is from a crystal oscillator (with amplification), not feedback from the drain circuit.  Frequency is the lowest ISM allocation at 6.78MHz.  Otherwise this is the same as other class-E circuits.

Power is somewhat limited so far, about 800 watts.  Hope to get a little higher.  With a fixed frequency, the coil must be tuned to achieve class-E operation before starting an arc.  Gate-drive frequency does not track increasing arc capacitance.  Larger arcs pull the coil farther out-of-tune.  The FET sees much more reactive power than real power.  To keep the FET within voltage and current ratings, FET reactive power can't get too high.  That makes real power even more limited.

I'm experimenting with a 4S2 (NiZn) ferrite for adjusting primary coil inductance.  Can't get more than about 1% frequency range (2% inductance range) before the ferrite gets too hot.  The clean (and more complex) solution to a fixed-frequency HFSSTC would be to use a PLL to start at a higher frequency, then lock to the desired fixed frequency once the arc is large enough.

Here's my simulation schematic.  The 3.3V pulse generator V3 simulates the crystal oscillator.  Amplifier stage is ZVS feeding a GDT.  GDT leakage inductance is the ZVS resonant inductance, with gate voltage opposite phase to GDT input due to this tuned leakage inductance.  FET is a 17A 1200V SiC NVH4L160N120SC1.


Breakout is a carbon rod following Steve Ward's example.  The arc wanders around the rod top and upper sides.  Not sure if this is due to the lower-than-typical frequency, or just that the breakout doesn't get hot enough for thermionic emission.  Any thoughts here?

/>
BTW, the backdrop in the video is a white wall with bright room illumination.  I've manually set camera exposure low to avoid arc wash-out.

Edit:  Fixed one schematic error.  I'd lowered breakout capacitance and forgot to add in the corresponding secondary coil capacitance, now as C5.
« Last Edit: May 24, 2021, 01:11:44 AM by davekni »
David Knierim

Offline Uspring

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Re: HFSSTC with fixed crystal-controlled frequency
« Reply #1 on: May 22, 2021, 02:20:26 PM »
Quote
The arc wanders around the rod top and upper sides.  Not sure if this is due to the lower-than-typical frequency, or just that the breakout doesn't get hot enough for thermionic emission.

There's presumably not enough heat for thermionic emission. But here is no real advantage to thermionic emission.The cathode fall voltage is larger for electron liberation by ion impact on the cathode, since that is comparatively inefficient and has to be followed by electron multiplication in the fall region. But in contrast to an arc lamp, we have a single ended arc with lots of voltage, so that some cathode fall voltage loss doesn't matter.
The carbon rod seems fairly well rounded with no preferred region of high curvature, a bit like a toroid, where arcs tend to wander around.
A courteous feature running the coil in the ISM band.

Offline Weston

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Re: HFSSTC with fixed crystal-controlled frequency
« Reply #2 on: May 22, 2021, 09:04:50 PM »
Looks cool!

I made a few 6.78MHz GaN class E coils a few years ago, although they were only a few hundred watts https://www.flickr.com/photos/63341195@N08/albums/72157650804366725

SiC should allow you to push out a lot more power.

What do your drain and gate waveforms look like?

One issue with these fixed frequency designs is that tuning is a balance between performance at full power and getting the arc to strike. I often wondered how hard it would be to add some additional circuit to strike the arc.

Resonant gate drive precludes frequency hopping over a wide range, but perhaps the transient Efield from a piezo ignitor or other HV source would be enough to get the arc to strike, sorta like how flash bulb triggering works?

Offline Steve Ward

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Re: HFSSTC with fixed crystal-controlled frequency
« Reply #3 on: May 23, 2021, 12:22:58 AM »
Thanks for making this and sharing it!

I'm impressed that it works well with fixed freq.  Could you share some waveforms during the operation?**  Seeing no extra snubber capacitance from D-S suggests you're likely seeing short, but relatively high amplitude, voltage pulses?  Usually the drain voltage is clamped from going negative by the body diode.  I add extra D-S capacitance when possible (usually about the same energy as Coss), to widen but shorten the drain voltage pulse, but its limited by the Q of the load, if too low, ZVS switching is lost. This is how my HFSSTC works over its limits in range, but i could imagine how fixed frequency would further hinder safe switching under different load conditions.

**You may already be aware, but for those who aren't, its good to realize that probing high frequency and high voltage can destroy probes at less than their rated AC voltage.  I use passive 100X probes rated for 2 or 5kV, and even they will not spec them to handle the ~1kV at 10MHZ that i subject them to, however they do seem to manage (maybe not so much long term). 
...
However, my Micsig differential probe promptly burned out part of its compensation network (which includes resistors in series with capacitors to fine tune the response).  I tried to alert them of this issue as they do not include a frequency de-rating for their probe, but it fell on deaf ears of their support people who insisted its 1300V rating was fine to 100MHZ!  Anyway, a typical probe with 20pF load capacitance probing an 800V peak-peak signal would see just about 1amp peak to peak, which is quite a lot for a probe!  The higher voltage probes can get down to just a few pF which seems to be key to their surviving, is my bet.  However, the micsig probe is only 2pF in single ended mode (one side of the probe at a stable voltage), and it still failed.  On the other hand, the relatively low cost P2301C is only rated for 50VAC at 10MHz despite its 5kVDC rating.  And even with 6.5pF input capacitance, its not looking great, but so far it's held up OK with ~1kVpk at ~9MHz.

Quote
I used that on my lower power ~200 watt HFSSTC. I tried other electrodes including carbon and like the
tungsten best. An iridium spark plug conductor also worked and didn't appear to erode like the tungsten.
It was wild watching some of the higher melting point metals melt in that arc.

With higher power levels, tungsten begins to flash a blinding white light.  I've melted a spot on a 1/4" tungsten rod with a ~1kW HFSSTC, during the event the rod was emitting incredible sounds like a tea kettle boiling over.  I wore a welding mask and sucked the gases out of the area with overhead hood. 

I know there's a lot of folks that really adore tungsten, but from a practical sense, carbon rod wins by a lot in terms of utility/cost.

Offline Da_Stier

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Re: HFSSTC with fixed crystal-controlled frequency
« Reply #4 on: May 23, 2021, 02:16:56 PM »
Hi David,

nice work, very impressive.
How do you deal with the frequency / impedance change if the arc is lit?
I built a similar coil, where I matched the primary to 50 Ohms impedance with a L network.
I drive the coil with a LDMOS power amplifier at fixed frequency.
However when the arc starts, the circuit is loaded enough to shift the impedance to where it won't work any more and even destroyed the LDMOS once.


Greetings,
Michael

Offline davekni

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Re: HFSSTC with fixed crystal-controlled frequency
« Reply #5 on: May 23, 2021, 08:56:02 PM »
I don't have a good place to clip a scope probe on the gate now.  I'd measured gate signal once earlier with drain voltage on.  It looks almost the same as with no drain power, excepting some high-frequency ringing, likely due to probe ground lead.  I captured and saved a gate waveform w/o drain power today, then separately a couple drain waveforms at 800W and 1100W.  All are triggered by a separate channel on one GDT input lead, so properly phased.  Here is a plot of the waveforms, with gate (tek00000.wfm) scaled by 10x (10V/div instead of 100V/div as shown for the drain waveforms).



Yes, I'm aware of scope probe voltage limitation at high frequency.  Initially used small capacitive dividers to probe AC-coupled.  Finally spent $200 for a Tek P5100 that is capable measuring the drain voltage properly.

Carbon is working well.  Tungsten glows white hot as Steve mentioned, and burns.  The one nice feature was the smaller-diameter tungsten (1.5mm) allowed an arc to start by itself.  I'd initially ground a point on the carbon rod.  That worked once, but the rod quickly eroded into a rounded end.  With the rounded end, manual starting is needed.  Otherwise I get an arc from the wire, as shown at the start of this new video:

/>
Here I ramp power to 1100 watts.  It briefly gets to 1200 watts, but current bounces around and drops a bit with time.  Most of the run is at 160Vdc and ~7Adc, up to 7.5Adc for a few seconds initially.

Steve:  Interesting to know that you use external drain-source capacitance.  I'd wondered about that and ran many simulations both with and without external capacitance.  In simulation, I could get a little more power with the external capacitor.  It lowered primary resonant impedance, reducing how far out-of-tune it became as the secondary arc load increased.  However, I liked the simplicity and cleanliness of using internal FET Cds only.  FET current is close to sine wave.  No sudden changes in current at zero Vds.  Even though this FET has dual source leads, I liked the idea of no sudden current transfer, avoiding the resulting ring in the parasitic inductance loop from FET to external drain-source capacitor.

Clearly I do have some ~80MHz harmonic showing up in the Vds waveform.  Haven't spent time looking for what is resonating at that frequency.

I did fry one Sic FET with a secondary flash-over during development.  About 1-ohm gate-source short.  Body diode works and the FET still functions (with pulsed gate voltage overcoming the 1-ohm short).  I haven't been able to figure out how the secondary coil flash-over could have induced excess gate voltage.  Has anyone seen SiC FETs fry due to excess drain power and/or voltage with the resulting damage being to the gate only?



This was relearning something I already knew well, that polyimide is prone to arc tracking.  It has long been banned in aircraft cable insulation for that reason, and I've had personal experience with 40V power on polyimide flex circuits.  If one spot overheats for whatever reason, polyimide carbonizes, making a conductive path that rapidly propagates.
« Last Edit: May 23, 2021, 09:05:55 PM by davekni »
David Knierim

Offline Steve Ward

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Re: HFSSTC with fixed crystal-controlled frequency
« Reply #6 on: June 13, 2021, 06:25:20 PM »
Quote
Steve:  Interesting to know that you use external drain-source capacitance.  I'd wondered about that and ran many simulations both with and without external capacitance.  In simulation, I could get a little more power with the external capacitor.  It lowered primary resonant impedance, reducing how far out-of-tune it became as the secondary arc load increased.  However, I liked the simplicity and cleanliness of using internal FET Cds only.  FET current is close to sine wave.  No sudden changes in current at zero Vds.  Even though this FET has dual source leads, I liked the idea of no sudden current transfer, avoiding the resulting ring in the parasitic inductance loop from FET to external drain-source capacitor.

I had the same line of thought (about snubber current vs fet channel current), and for a period of time I suspected the added D-S capacitance was causing my circuit to self-oscillate in a worse way due to the interrupted current through the common source inductance (it blew up once and there was unusual ringing observed at the gate). However, in practice it seems to work fine despite a little extra ringing.  I try to keep the extra Cds about equal in charge to the fet's Qoss, effectively doubling the charge of the fet alone, all else being equal this should allow for twice the input current for the same peak voltage.  For the SiC JFET cascode that i use, the extra Cds should help reduce switch-off losses which are the dominant source of energy loss, i think, for most class E.  Other SiC Fet technology might not be as limited in switch-off speed, so perhaps you wouldn't see much gain from the extra Cds.  Also, i use the 4-lead package for lower source inductance.

Noticing a few things about your design - the secondary Fres is significantly higher than the operating frequency, and so I think this mode of operation, primary-resonant, is what provides graceful operation over wide power range with a fixed frequency.  Perhaps, like my HFSSTCs, once the arc capacitance is big enough to bring the secondary Fres to the actual operating frequency, the ZVS turn-on is lost.

Thanks for the waveforms, I also see similar higher frequency ringing in mine but not as pronounced on the drain voltage like that. I assumed in my case it might be ringing of the Cds internal vs snubber with any inductance between them, but you dont have that circuit... hmmm

Offline davekni

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Re: HFSSTC with fixed crystal-controlled frequency
« Reply #7 on: June 27, 2021, 05:18:14 AM »
Quote
Thanks for the waveforms, I also see similar higher frequency ringing in mine but not as pronounced on the drain voltage like that. I assumed in my case it might be ringing of the Cds internal vs snubber with any inductance between them, but you dont have that circuit... hmmm

My guess is a higher-order resonance of winding capacitance and inductance happens to hit the 12th harmonic of 6.78MHz.  Or perhaps wiring inductance and parasitic coil capacitance.  Frequency is too high to be the upper pole of the coupled inductors.  (My new 13.56MHz version did initially hit upper-pole as second harmonic of 13.56MHz fundamental.)
David Knierim

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Re: HFSSTC with fixed crystal-controlled frequency
« Reply #7 on: June 27, 2021, 05:18:14 AM »

 


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