GDT output buffer

[davekni]

For years I've pondered the trade-offs between GDTs (simple) and isolated gate driver chips (more complex, including isolated supplies for each gate).  For my new QCW experiment platform, decided on a compromise: GDT with simple output buffer.  Rising edge behavior is standard GDT output through damping resistor.  Falling edge is a local PFET shorting Vge.

This is intended for IGBTs with no internal gate resistors (all TO247 devices I've seen and some smaller bricks).  For these IGBTs, there is no need for negative Vge as long as gate drive impedance is low.  In normal GDT drive, Vge falling edge speed is limited by GDT leakage inductance.  With buffer, GDT has light load on falling edges, so is fast.  For high frequency CW applications where gate power is a significant concern, avoiding negative Vge reduces power by ideally 4x.  Reality here is about 3x.

Posting this under "DRSSTC" category, though it could be useful for induction heating or other applications.

Buffer schematic.  One needed for each IGBT (or parallel set of IGBTs):



R1 is the normal rising-edge damping resistor for GDT output, 9.4 ohms in this example.  R1 has a series diode D1 to prevent conduction when GDT output is negative (when Vge is zero).  PFET M1 (IRFZ24) provides low-impedance shorting of Vge when GDT output is negative.  D2 limits PFET Vgs to spec +-20V.  Would likely work fine without D2.  R2 provides damping for PFET Vgs and limits current through D2 during any GDT undershoot.  I use this circuit with +-19V into GDT.  D3 clamps Vge under any anomalous conditions, especially ESD during construction and handling.

Here's my first H-Bridge using four of above buffer circuits and two GDTs (one per half-bridge).  Circuit is simple enough to construct on raw double-sided copper-clad board and dremel-tool cuts.  IRFZ24's are surface-mounted on one side and remaining parts on other side.  R1 is an array of 1206 SMD resistors here to handle power of continuous 500kHz operation.  Power is significant even though much less than it would be with +-19Vge drive.  IGBTs here are parallel pairs of FGH75T65SHDTLN4, which are in 4-lead TO247 packages (Kelvin emitter lead).  Power ECB is per my low-parasitic-inductance tutorial with bypass caps on back side.



Only issue so far with actual use is that these IGBTs have roughly the same turn-on and turn-off times, at least in my testing.  With this buffer's very fast turn-off (~20ns from UD output to Vge falling), turn-on delay (dead time) can't be set low enough.  Reducing R1 below 9.4 ohms causes more overshoot on Vge.  That would be OK for low duty cycles, but increases gate drive power dissipation for CW cases.  If excess dead-time becomes too problematic, I'll need to make new GDTs with even lower leakage inductance to allow lower R1 values.

Below are a bunch of scope captures.  Including all these for a second purpose, as an explanation of H-bridge output triple-transitions.  Ideally, I'd get rid of triple-transitions by reducing dead-time.  Only other option is to increase phase lead.  However, at ~480kHz, additional phase lead causes IGBT turn-off at high current, since current slew rate is so high.

For all below scope captures:
Ch1 (black) is H-Bridge output, differential between two outputs, 20V/div.
Ch2 (green) is H-Bridge (primary) current at 50A/div.
Ch3 (red) is Vge at 5V/div.
Ch4 (cyan) is one output from UD-like driver.

Near end of a small burst at +-190A:









Notice the triple-transitions in H-bridge output.  Initial transition is at IGBT turn-off, while that IGBT pair had been conducting current.  A bit later current reverses polarity, pulling H-bridge output voltage back in the opposite direction.  As voltage gets about half-way back, opposite IGBT pair turns on, pulling H-bridge output voltage to desired new state.


Start of burst where current is low:









Notice that above low-current captures have no triple-transition.  H-bridge output transitions only after opposite IGBT pair turns on.  That's because there is insufficient current to cause a voltage transition at turn-off.  Below is a capture at mid-current, enough current for output transition at IGBT turn-off, but barely enough to cause a hint of triple-transition:




Finally, here's a capture at the end of a burst where residual primary current is causing H-bridge output transitions.  GDT input is at 0V (both GDT inputs high in my case rather than more normal both-low).  IGBT Crss (collector-to-gate capacitance) causes small swings in Vge.  Positive swing is limited by PFET threshold voltage.  PFET must be selected to have threshold voltage well below IGBT's threshold voltage.

[Hydron]

I didn't realise that you didn't need negative Vge for the TO-247 parts - thanks for pointing this out and sharing the circuit! I'd wanted to try this sort of driver for a while, but the complexity of generating a negative rail from the GDT output in addition to the turn-off P-FET always put me off - this is much simpler. I'm sticking with GDT operation rather than isolated driver chips for the same reasons you mentioned - eventually I'll be driving 16 IGBTs, and GDTs are just way simpler and cheaper than all those isolated supplies (I'm also gonna have a crack at making a planar GDT so I can avoid having to wind the things).

I gave the buffer circuit a bit of a go over the long weekend with some parts I had lying around; while I didn't get a chance to optimise it properly it certainly seemed to work OK, with the possible exception of some oscillation when hard-switching high currents (~200A so pushing pretty hard, and hard to tell if the waveforms were actually real or just pickup on the probes). I'm certainly going to add it as a stuffing option to my next half-bridge board spin.

The other potential advantage of this style of gate drive is that it allows for better "active clamping" to prevent over-voltage on turn-off. If you put a TVS of appropriate rating between gate and collector then when the Vce goes over the TVS breakdown voltage it will start to conduct current into the gate and slow the turnoff and reduce the over-voltage peak, but will also fight the GDT via the gate resistor, reducing the effectiveness and increasing dissipation. With the output buffer then you can put the TVS going to the PFET gate instead, which will have the same effect but driving a higher impedance (50 ohms in this case).

As for low-leakage GDTs, I've had decent results using RG-174 as windings on a high-Al toroid - only need 4 or 5 turns, and can use the shield as a primary and core as a secondary for super tight coupling. Putting the drive FETs right next to the GDT and using ribbon cable (with multiple pairs in parallel) between the GDT and IGBTs then allows for low inductance from the driver to the gates, and hopefully reasonably low turn-on resistors (otherwise you wipe out all the good you do with the transformer by adding inductance afterwards).

How have you found the FGH75T65SHDTLN4 to behave btw? Any significant improvement from say FGY75N60SMD or similar 3-pin devices? I like the idea of the 4-pin devices (and it makes gate connections easier) but they're often more expensive and it's hard to go past the big chunky die size (thus lower thermal resistance) and proven performance of the 3-pin ONSemi parts (plus the FGH75T65SHDTLN4 datasheet doesn't seem to have numbers for Rg <15 ohms!).

[davekni]

I didn't realise that you didn't need negative Vge for the TO-247 parts - thanks for pointing this out and sharing the circuit! I'd wanted to try this sort of driver for a while, but the complexity of generating a negative rail from the GDT output in addition to the turn-off P-FET always put me off - this is much simpler. I'm sticking with GDT operation rather than isolated driver chips for the same reasons you mentioned - eventually I'll be driving 16 IGBTs, and GDTs are just way simpler and cheaper than all those isolated supplies (I'm also gonna have a crack at making a planar GDT so I can avoid having to wind the things).

Exciting to see some interest in this.  Hope you post whatever variation you end up using.
Planar GDT with "windings" on opposite sides of a thin ECB should keep leakage inductance low.

The other potential advantage of this style of gate drive is that it allows for better "active clamping" to prevent over-voltage on turn-off. If you put a TVS of appropriate rating between gate and collector then when the Vce goes over the TVS breakdown voltage it will start to conduct current into the gate and slow the turnoff and reduce the over-voltage peak, but will also fight the GDT via the gate resistor, reducing the effectiveness and increasing dissipation. With the output buffer then you can put the TVS going to the PFET gate instead, which will have the same effect but driving a higher impedance (50 ohms in this case).

Have you tried active clamping with IGBTs before?  I'd be concerned about delays in turn-on and turn-off causing issues.

As for low-leakage GDTs, I've had decent results using RG-174 as windings on a high-Al toroid - only need 4 or 5 turns, and can use the shield as a primary and core as a secondary for super tight coupling.

Such 50-ohm coax should have ~250nH/m leakage inductance.  The twisted pairs I've measured were around 660nH/m.  Would take three paralleled pairs to get below leakage inductance of a single 50-ohm coax.  Lower impedance coax would be even better.  Some laptop supplies and wall-wart supplies use coaxial construction for DC output cable.  Not good for RF, but usually lower impedance and correspondingly lower inductance/distance.  Not sure where to find such cable beyond random scraps in my junk stashes.
For my only IGBT brick build (low-frequency QCW), I went for low leakage inductance at some risk of insulation breakdown.  Twisted 27AWG magnet wire to reduce inductance per pair, then used 5 pairs in parallel for each gate (20 pairs total for primary), 2 turns on an E55 core pair.

BTW, with this circuit, a little bit of leakage inductance can be advantageous.  For rising Vge edges, a critically-damped LRC waveform shape has steeper rise rate for a given delay.  Falling delay is minimally affected due to the FET's lower input capacitance.  For this purpose, inductance in GDT output wires is best.  Leakage inductance on input wires or otherwise common between high and low sides will delay fall time a bit.  (I kept paralleled GDT primary pairs twisted separately for this reason.)  For this QCW build, I thought I would want ~200ns of dead time.  Built GDT for leakage inductance to match that (critically-damped LRC), so didn't make effort to minimize.

Putting the drive FETs right next to the GDT and using ribbon cable (with multiple pairs in parallel) between the GDT and IGBTs then allows for low inductance from the driver to the gates, and hopefully reasonably low turn-on resistors (otherwise you wipe out all the good you do with the transformer by adding inductance afterwards).

Yes, I've used ribbon cable that way too.  Easy to parallel pairs with the 2x square-pin connectors.  Or multiple paralleled twisted pairs.  And close spacing as you say.

How have you found the FGH75T65SHDTLN4 to behave btw? Any significant improvement from say FGY75N60SMD or similar 3-pin devices? I like the idea of the 4-pin devices (and it makes gate connections easier) but they're often more expensive and it's hard to go past the big chunky die size (thus lower thermal resistance) and proven performance of the 3-pin ONSemi parts (plus the FGH75T65SHDTLN4 datasheet doesn't seem to have numbers for Rg <15 ohms!).

So far FGH75T65SHDTLN4  are working well for my 485kHz QCW.  This 4-pin version appears to have been introduced and then dropped soon after.  Likely customized for some large customer who then canceled a project.  I like 4 pins, but purchased this mostly because it was cheap and fast.  For a 3-pin version with specs down to 3ohm external gate resistance, FGH75T65SHD appears to have identical die inside, continued availability, and a final-version spec.  As you point out, there are many somewhat-similar variations.  My criteria for this part was fast switching, reasonably fast diode, and diode temperature coefficient that allowed paralleling.  Other parts have lower Vf but also somewhat slower switching.  Saw one newer-generation part that seemed somewhat better overall except that thermal resistance was higher (presumably smaller die).

[Hydron]

Whipped up some new PCBs for my half-bridge modules - 4 layers instead of two (shipping costs almost as much as the 4-layer PCBs these days, so no reason not to go with 4) and the GDT output buffer as a stuff option.

I've only made up one board and am about to go on holiday for a couple of weeks, but either the board or the buffer (which I placed on this one board) or both has made a spectacular difference to overshoot on turn-off. I'll try and build another if I have time with the "conventional" (un-buffered) option as a comparison to take the PCB change out of the equation. Will post pics etc (or at least PCB renders and design files) when I get a chance.

Your comment about GDT inductance helping turn-on is an interesting one, I'll need to make some measurements and see if I can model what the scope sees, and then do some tweaking. The ribbon cable output from the GDT might be a good way to tweak leakage L actually - snip some of the parallel pairs until it matches the desired inductance.

[曹靖]

My QCW uses a slower switching speed and a larger IGBT package, but it has never exploded. I ran it at 420KHz and its peak current reached 200A, outputting a 95-inch linear arc IGBT for the secondary output. The IGBT still works well

[Hydron]

Good to know you're getting such good results with slower IGBTs - are you soft switching them and using a buck converter to modulate the QCW output?

My comments about over-shoot on switch-off were about hard-switching - a combination of layout/package inductance and non-instant conduction of the freewheeling diode in the other IGBT package (forward recovery time, it's a thing for non-schottky diodes albeit not often specified) means that there is an overshoot when hard-switching large currents (e.g. 200A) fast, as is needed for a phase-shift QCW coil.

[曹靖]

Yes, the buck converter I used to provide ramp voltage to the entire bridge is a soft switch~BUCK. I used eight 160N60UFD switches, four as IGBT switches, and the other four as freewheeling diodes. Hard switch phase-shifting drive may not be suitable for this type of transistor. Sorry, (_)>Also, I want to attach a picture of the QCWDRSTC effect I made with this full bridge~Show off (๑> ؂< ๑）

[Hydron]

Yes, the buck converter I used to provide ramp voltage to the entire bridge is a soft switch~BUCK. I used eight 160N60UFD switches, four as IGBT switches, and the other four as freewheeling diodes. Hard switch phase-shifting drive may not be suitable for this type of transistor. Sorry, (_)>Also, I want to attach a picture of the QCWDRSTC effect I made with this full bridge~Show off (๑> ؂< ๑）

Fair enough showing off - impressive result.

Maybe best to make a new thread to document your coil and attach photos etc - this one is more specifically about using a buffer with a GDT for IGBT drive.

[Hydron]

I've only made up one board and am about to go on holiday for a couple of weeks, but either the board or the buffer (which I placed on this one board) or both has made a spectacular difference to overshoot on turn-off. I'll try and build another if I have time with the "conventional" (un-buffered) option as a comparison to take the PCB change out of the equation. Will post pics etc (or at least PCB renders and design files) when I get a chance.

Had a very quick investigation, looks like the improvement was a bit of column A, bit of column B. New PCB seems to have made the biggest change, but the buffer improves it even more. See attached pics, first is with the buffer (ignore the yellow trace, that's from the other igbt and the diff probe is picking up a bunch of nasty stuff from the other half bridge), second is without. Orange is Vce, green is Vge, blue is current. Will upload pics of the half bridge board when I'm not posting from my phone.

[davekni]

Had a very quick investigation, looks like the improvement was a bit of column A, bit of column B. New PCB seems to have made the biggest change, but the buffer improves it even more. See attached pics, first is with the buffer (ignore the yellow trace, that's from the other igbt and the diff probe is picking up a bunch of nasty stuff from the other half bridge), second is without. Orange is Vce, green is Vge, blue is current. Will upload pics of the half bridge board when I'm not posting from my phone.

Thank you for the update and scope traces!  BTW, even if Vge isn't dramatically better, buffer also reduce gate drive power by ~3x, relevant for high duty cycle uses.

[Hydron]

Half bridge pics attached. BNCs are for scoping Vge and Vce on the low side IGBT.